[llvm] f2e4423 - [RISCV] Clean up RISCVInstrInfoXTHead.td to look like the same style with other td file. NFC.
Jim Lin via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 30 23:39:39 PDT 2023
Author: Jim Lin
Date: 2023-07-31T14:38:21+08:00
New Revision: f2e44238ee35f9fb6aa6d07b07f3d6469a5e9416
URL: https://github.com/llvm/llvm-project/commit/f2e44238ee35f9fb6aa6d07b07f3d6469a5e9416
DIFF: https://github.com/llvm/llvm-project/commit/f2e44238ee35f9fb6aa6d07b07f3d6469a5e9416.diff
LOG: [RISCV] Clean up RISCVInstrInfoXTHead.td to look like the same style with other td file. NFC.
Unify indent rule and add one blank line after comment block.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 8f7343faf5f2e2..8d18143595e1d1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -14,25 +14,30 @@
// T-HEAD specific DAG Nodes.
//===----------------------------------------------------------------------===//
-def SDT_LoadPair : SDTypeProfile<2, 2,
- [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 3>, SDTCisPtrTy<2>, SDTCisVT<3, XLenVT>]>;
-def SDT_StorePair : SDTypeProfile<0, 4,
- [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 3>, SDTCisPtrTy<2>, SDTCisVT<3, XLenVT>]>;
+def SDT_LoadPair : SDTypeProfile<2, 2, [SDTCisSameAs<0, 1>,
+ SDTCisSameAs<1, 3>,
+ SDTCisPtrTy<2>,
+ SDTCisVT<3, XLenVT>]>;
+def SDT_StorePair : SDTypeProfile<0, 4, [SDTCisSameAs<0, 1>,
+ SDTCisSameAs<1, 3>,
+ SDTCisPtrTy<2>,
+ SDTCisVT<3, XLenVT>]>;
def th_lwud : SDNode<"RISCVISD::TH_LWUD", SDT_LoadPair,
- [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+ [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def th_lwd : SDNode<"RISCVISD::TH_LWD", SDT_LoadPair,
- [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+ [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def th_ldd : SDNode<"RISCVISD::TH_LDD", SDT_LoadPair,
- [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
+ [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
def th_swd : SDNode<"RISCVISD::TH_SWD", SDT_StorePair,
- [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+ [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def th_sdd : SDNode<"RISCVISD::TH_SDD", SDT_StorePair,
- [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
+ [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
//===----------------------------------------------------------------------===//
// Instruction class templates
//===----------------------------------------------------------------------===//
+
class THInstVdotVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
string opcodestr, string argstr>
: RVInstVV<funct6, opv, outs, ins, opcodestr, argstr> {
@@ -64,7 +69,7 @@ class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "XTHeadBa",
- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class THShiftALU_rri<bits<3> funct3, string opcodestr>
: RVInstR<0, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
(ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
@@ -75,7 +80,7 @@ class THShiftALU_rri<bits<3> funct3, string opcodestr>
}
let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "XTHeadBb",
- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
: RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
(ins GPR:$rs1, uimmlog2xlen:$shamt),
@@ -97,7 +102,7 @@ class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
}
let Predicates = [HasVendorXTHeadBb, IsRV64], DecoderNamespace = "XTHeadBb",
- hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
class THShiftW_ri<bits<7> funct7, bits<3> funct3, string opcodestr>
: RVInstIShiftW<funct7, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
(ins GPR:$rs1, uimm5:$shamt),
@@ -122,7 +127,7 @@ class THMulAccumulate_rr<bits<7> funct7, string opcodestr>
}
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
- hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+ hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
class THLoadPair<bits<5> funct5, string opcodestr>
: RVInstR<!shl(funct5, 2), 0b100, OPC_CUSTOM_0,
(outs GPR:$rd, GPR:$rs2),
@@ -135,7 +140,7 @@ class THLoadPair<bits<5> funct5, string opcodestr>
}
let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
- hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+ hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
class THStorePair<bits<5> funct5, string opcodestr>
: RVInstR<!shl(funct5, 2), 0b101, OPC_CUSTOM_0,
(outs),
@@ -217,6 +222,7 @@ class THStoreUpdate<bits<5> funct5, string opcodestr>
// Combination of instruction classes.
// Use these multiclasses to define instructions more easily.
//===----------------------------------------------------------------------===//
+
multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {
def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx">;
}
@@ -229,10 +235,10 @@ multiclass THVdotVMAQA<string opcodestr, bits<6> funct6> {
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//
-let Predicates = [HasVendorXTHeadBa] in {
+
+let Predicates = [HasVendorXTHeadBa] in
def TH_ADDSL : THShiftALU_rri<0b001, "th.addsl">,
Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
-} // Predicates = [HasVendorXTHeadBa]
let Predicates = [HasVendorXTHeadBb] in {
def TH_SRRI : THShift_ri<0b00010, 0b001, "th.srri">;
@@ -249,20 +255,19 @@ def TH_SRRIW : THShiftW_ri<0b0001010, 0b001, "th.srriw">;
def TH_REVW : THRev_r<0b10010, 0b00, "th.revw">;
} // Predicates = [HasVendorXTHeadBb, IsRV64]
-let Predicates = [HasVendorXTHeadBs], DecoderNamespace = "XTHeadBs" in {
-let IsSignExtendingOpW = 1 in
+let Predicates = [HasVendorXTHeadBs], DecoderNamespace = "XTHeadBs",
+ IsSignExtendingOpW = 1 in
def TH_TST : RVBShift_ri<0b10001, 0b001, OPC_CUSTOM_0, "th.tst">,
Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
-} // Predicates = [HasVendorXTHeadBs]
let Predicates = [HasVendorXTHeadCondMov] in {
-def TH_MVEQZ : THCondMov_rr<0b0100000, "th.mveqz">;
-def TH_MVNEZ : THCondMov_rr<0b0100001, "th.mvnez">;
+def TH_MVEQZ : THCondMov_rr<0b0100000, "th.mveqz">;
+def TH_MVNEZ : THCondMov_rr<0b0100001, "th.mvnez">;
} // Predicates = [HasVendorXTHeadCondMov]
let Predicates = [HasVendorXTHeadMac] in {
-def TH_MULA : THMulAccumulate_rr<0b0010000, "th.mula">;
-def TH_MULS : THMulAccumulate_rr<0b0010001, "th.muls">;
+def TH_MULA : THMulAccumulate_rr<0b0010000, "th.mula">;
+def TH_MULS : THMulAccumulate_rr<0b0010001, "th.muls">;
} // Predicates = [HasVendorXTHeadMac]
let Predicates = [HasVendorXTHeadMac], IsSignExtendingOpW = 1 in {
@@ -286,124 +291,124 @@ def TH_LWD : THLoadPair<0b11100, "th.lwd">,
}
let Predicates = [HasVendorXTHeadMemPair, IsRV64] in {
-def TH_LDD : THLoadPair<0b11111, "th.ldd">,
- Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
-def TH_SDD : THStorePair<0b11111, "th.sdd">,
- Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;
+def TH_LDD : THLoadPair<0b11111, "th.ldd">,
+ Sched<[WriteLDD, WriteLDD, ReadMemBase]>;
+def TH_SDD : THStorePair<0b11111, "th.sdd">,
+ Sched<[WriteSTD, WriteSTD, ReadStoreData, ReadMemBase]>;
}
let Predicates = [HasVendorXTHeadMemIdx], DecoderNamespace = "XTHeadMemIdx" in {
// T-Head Load/Store + Update instructions.
def TH_LBIA : THLoadUpdate<0b00011, "th.lbia">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LBIB : THLoadUpdate<0b00001, "th.lbib">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LBUIA : THLoadUpdate<0b10011, "th.lbuia">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LBUIB : THLoadUpdate<0b10001, "th.lbuib">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LHIA : THLoadUpdate<0b00111, "th.lhia">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LHIB : THLoadUpdate<0b00101, "th.lhib">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LHUIA : THLoadUpdate<0b10111, "th.lhuia">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LHUIB : THLoadUpdate<0b10101, "th.lhuib">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LWIA : THLoadUpdate<0b01011, "th.lwia">,
- Sched<[WriteLDW, ReadMemBase]>;
+ Sched<[WriteLDW, ReadMemBase]>;
def TH_LWIB : THLoadUpdate<0b01001, "th.lwib">,
- Sched<[WriteLDW, ReadMemBase]>;
+ Sched<[WriteLDW, ReadMemBase]>;
def TH_SBIA : THStoreUpdate<0b00011, "th.sbia">,
- Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
def TH_SBIB : THStoreUpdate<0b00001, "th.sbib">,
- Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
def TH_SHIA : THStoreUpdate<0b00111, "th.shia">,
- Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
def TH_SHIB : THStoreUpdate<0b00101, "th.shib">,
- Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
def TH_SWIA : THStoreUpdate<0b01011, "th.swia">,
- Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
def TH_SWIB : THStoreUpdate<0b01001, "th.swib">,
- Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
// T-Head Load/Store Indexed instructions.
def TH_LRB : THLoadIndexed<GPR, 0b00000, "th.lrb">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LRBU : THLoadIndexed<GPR, 0b10000, "th.lrbu">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LURB : THLoadIndexed<GPR, 0b00010, "th.lurb">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LURBU : THLoadIndexed<GPR, 0b10010, "th.lurbu">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LRH : THLoadIndexed<GPR, 0b00100, "th.lrh">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LRHU : THLoadIndexed<GPR, 0b10100, "th.lrhu">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LURH : THLoadIndexed<GPR, 0b00110, "th.lurh">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LURHU : THLoadIndexed<GPR, 0b10110, "th.lurhu">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LRW : THLoadIndexed<GPR, 0b01000, "th.lrw">,
- Sched<[WriteLDW, ReadMemBase]>;
+ Sched<[WriteLDW, ReadMemBase]>;
def TH_LURW : THLoadIndexed<GPR, 0b01010, "th.lurw">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_SRB : THStoreIndexed<GPR, 0b00000, "th.srb">,
- Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTB, ReadStoreData, ReadMemBase]>;
def TH_SURB : THStoreIndexed<GPR, 0b00010, "th.surb">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_SRH : THStoreIndexed<GPR, 0b00100, "th.srh">,
- Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTH, ReadStoreData, ReadMemBase]>;
def TH_SURH : THStoreIndexed<GPR, 0b00110, "th.surh">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_SRW : THStoreIndexed<GPR, 0b01000, "th.srw">,
- Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
def TH_SURW : THStoreIndexed<GPR, 0b01010, "th.surw">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
}
let Predicates = [HasVendorXTHeadMemIdx, IsRV64], DecoderNamespace = "XTHeadMemIdx" in {
// T-Head Load/Store + Update instructions.
def TH_LWUIA : THLoadUpdate<0b11011, "th.lwuia">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LWUIB : THLoadUpdate<0b11001, "th.lwuib">,
- Sched<[WriteLDH, ReadMemBase]>;
+ Sched<[WriteLDH, ReadMemBase]>;
def TH_LDIA : THLoadUpdate<0b01111, "th.ldia">,
- Sched<[WriteLDW, ReadMemBase]>;
+ Sched<[WriteLDW, ReadMemBase]>;
def TH_LDIB : THLoadUpdate<0b01101, "th.ldib">,
- Sched<[WriteLDW, ReadMemBase]>;
+ Sched<[WriteLDW, ReadMemBase]>;
def TH_SDIA : THStoreUpdate<0b01111, "th.sdia">,
- Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
def TH_SDIB : THStoreUpdate<0b01101, "th.sdib">,
- Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
// T-Head Load/Store Indexed instructions.
def TH_LRWU : THLoadIndexed<GPR, 0b11000, "th.lrwu">,
- Sched<[WriteLDW, ReadMemBase]>;
+ Sched<[WriteLDW, ReadMemBase]>;
def TH_LURWU : THLoadIndexed<GPR, 0b11010, "th.lurwu">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_LRD : THLoadIndexed<GPR, 0b01100, "th.lrd">,
- Sched<[WriteLDW, ReadMemBase]>;
+ Sched<[WriteLDW, ReadMemBase]>;
def TH_LURD : THLoadIndexed<GPR, 0b01110, "th.lurd">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
def TH_SRD : THStoreIndexed<GPR, 0b01100, "th.srd">,
- Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
+ Sched<[WriteSTW, ReadStoreData, ReadMemBase]>;
def TH_SURD : THStoreIndexed<GPR, 0b01110, "th.surd">,
- Sched<[WriteLDB, ReadMemBase]>;
+ Sched<[WriteLDB, ReadMemBase]>;
}
// T-Head Load/Store Indexed instructions for floating point registers.
@@ -469,6 +474,7 @@ defset list<VTypeInfoToWide> AllQuadWidenableInt8NoVLMulVectors = {
// Combination of instruction classes.
// Use these multiclasses to define instructions more easily.
//===----------------------------------------------------------------------===//
+
multiclass VPseudoVMAQA_VV_VX {
foreach m = MxListTHVdot in {
// TODO: Add Sched
@@ -517,6 +523,7 @@ multiclass VPatTernaryVMAQA_VV_VX<string intrinsic, string instruction,
//===----------------------------------------------------------------------===//
// Pseudo-instructions and codegen patterns
//===----------------------------------------------------------------------===//
+
let Predicates = [HasVendorXTHeadBa] in {
def : Pat<(add (XLenVT GPR:$rs1), (shl GPR:$rs2, uimm2:$uimm2)),
(TH_ADDSL GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>;
@@ -686,10 +693,14 @@ defm PseudoTHVdotVMAQASU : VPseudoVMAQA_VV_VX;
defm PseudoTHVdotVMAQAUS : VPseudoVMAQA_VX;
let Predicates = [HasVendorXTHeadVdot] in {
-defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa", "PseudoTHVdotVMAQA", AllQuadWidenableInt8NoVLMulVectors>;
-defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU", AllQuadWidenableInt8NoVLMulVectors>;
-defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",AllQuadWidenableInt8NoVLMulVectors>;
-defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus", "PseudoTHVdotVMAQAUS",AllQuadWidenableInt8NoVLMulVectors>;
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqa", "PseudoTHVdotVMAQA",
+ AllQuadWidenableInt8NoVLMulVectors>;
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqau", "PseudoTHVdotVMAQAU",
+ AllQuadWidenableInt8NoVLMulVectors>;
+defm : VPatTernaryVMAQA_VV_VX<"int_riscv_th_vmaqasu","PseudoTHVdotVMAQASU",
+ AllQuadWidenableInt8NoVLMulVectors>;
+defm : VPatTernaryVMAQA_VX<"int_riscv_th_vmaqaus", "PseudoTHVdotVMAQAUS",
+ AllQuadWidenableInt8NoVLMulVectors>;
}
def uimm2_3_XFORM : SDNodeXForm<imm, [{
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