[llvm] 56b54ed - [RISCV] Combine setOperationAction code for ISD::CTLZ for Zbb and XTheadBB. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-30T23:01:59-07:00
New Revision: 56b54eda52ef03cbfa7948f78f799de29dc4ae0b

URL: https://github.com/llvm/llvm-project/commit/56b54eda52ef03cbfa7948f78f799de29dc4ae0b
DIFF: https://github.com/llvm/llvm-project/commit/56b54eda52ef03cbfa7948f78f799de29dc4ae0b.diff

LOG: [RISCV] Combine setOperationAction code for ISD::CTLZ for Zbb and XTheadBB. NFC

This avoids needing to change ISD::CTLZ back to Legal after earlier
code set it to Expand.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6dfe3704678479..66eb99060264ea 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -324,19 +324,19 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
     if (Subtarget.is64Bit())
       setOperationAction(
-          {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF},
+          {ISD::CTTZ, ISD::CTTZ_ZERO_UNDEF},
           MVT::i32, Custom);
   } else {
-    setOperationAction({ISD::CTTZ, ISD::CTLZ, ISD::CTPOP}, XLenVT, Expand);
+    setOperationAction({ISD::CTTZ, ISD::CTPOP}, XLenVT, Expand);
   }
 
-  if (Subtarget.hasVendorXTHeadBb()) {
-    setOperationAction(ISD::CTLZ, XLenVT, Legal);
-
+  if (Subtarget.hasStdExtZbb() || Subtarget.hasVendorXTHeadBb()) {
     // We need the custom lowering to make sure that the resulting sequence
     // for the 32bit case is efficient on 64bit targets.
     if (Subtarget.is64Bit())
       setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
+  } else {
+    setOperationAction(ISD::CTLZ, XLenVT, Expand);
   }
 
   if (Subtarget.is64Bit())