[llvm] 76f0d18 - [AArch64] Regenerate arm64-vabs.ll, arm64-subvector-extend.ll and some mir tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 30 08:51:06 PDT 2023
Author: David Green
Date: 2023-07-30T16:51:01+01:00
New Revision: 76f0d186d628311f8436bac4b267a571a7086532
URL: https://github.com/llvm/llvm-project/commit/76f0d186d628311f8436bac4b267a571a7086532
DIFF: https://github.com/llvm/llvm-project/commit/76f0d186d628311f8436bac4b267a571a7086532.diff
LOG: [AArch64] Regenerate arm64-vabs.ll, arm64-subvector-extend.ll and some mir tests. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
llvm/test/CodeGen/AArch64/arm64-vabs.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
index 9aeff9f3b7846b..472b09a3d78cb3 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ctpop.mir
@@ -15,6 +15,7 @@ body: |
; CHECK-NEXT: %ctpop:_(<8 x s8>) = G_CTPOP %copy(<8 x s8>)
; CHECK-NEXT: $d0 = COPY %ctpop(<8 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
+ ;
; CHECK-CSSC-LABEL: name: v8s8_legal
; CHECK-CSSC: liveins: $d0
; CHECK-CSSC-NEXT: {{ $}}
@@ -41,6 +42,7 @@ body: |
; CHECK-NEXT: %ctpop:_(<16 x s8>) = G_CTPOP %copy(<16 x s8>)
; CHECK-NEXT: $q0 = COPY %ctpop(<16 x s8>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ;
; CHECK-CSSC-LABEL: name: v16s8_legal
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
@@ -70,6 +72,7 @@ body: |
; CHECK-NEXT: %ctpop:_(s32) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlv), [[CTPOP]](<8 x s8>)
; CHECK-NEXT: $w0 = COPY %ctpop(s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ;
; CHECK-CSSC-LABEL: name: s32_lower
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -99,6 +102,7 @@ body: |
; CHECK-NEXT: %ctpop:_(s64) = G_ZEXT [[INT]](s32)
; CHECK-NEXT: $x0 = COPY %ctpop(s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
+ ;
; CHECK-CSSC-LABEL: name: s64_lower
; CHECK-CSSC: liveins: $x0
; CHECK-CSSC-NEXT: {{ $}}
@@ -134,6 +138,7 @@ body: |
; CHECK-NEXT: $x0 = COPY [[MV1]](s64)
; CHECK-NEXT: $x1 = COPY [[C1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
+ ;
; CHECK-CSSC-LABEL: name: s128_lower
; CHECK-CSSC: liveins: $x0, $x1
; CHECK-CSSC-NEXT: {{ $}}
@@ -176,6 +181,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ;
; CHECK-CSSC-LABEL: name: widen_s16
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -214,6 +220,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ;
; CHECK-CSSC-LABEL: name: widen_s8
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -252,6 +259,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ;
; CHECK-CSSC-LABEL: name: widen_s3
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -289,6 +297,7 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[INT]](s32)
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
+ ;
; CHECK-CSSC-LABEL: name:
diff erent_sizes
; CHECK-CSSC: liveins: $w0
; CHECK-CSSC-NEXT: {{ $}}
@@ -323,6 +332,7 @@ body: |
; CHECK-NEXT: [[INT:%[0-9]+]]:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[CTPOP]](<16 x s8>)
; CHECK-NEXT: $q0 = COPY [[INT]](<8 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ;
; CHECK-CSSC-LABEL: name: custom_8x16
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
@@ -355,6 +365,7 @@ body: |
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[INT]](<8 x s16>)
; CHECK-NEXT: $q0 = COPY [[INT1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ;
; CHECK-CSSC-LABEL: name: custom_4x32
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
@@ -389,6 +400,7 @@ body: |
; CHECK-NEXT: [[INT2:%[0-9]+]]:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[INT1]](<4 x s32>)
; CHECK-NEXT: $q0 = COPY [[INT2]](<2 x s64>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ;
; CHECK-CSSC-LABEL: name: custom_2x64
; CHECK-CSSC: liveins: $q0
; CHECK-CSSC-NEXT: {{ $}}
@@ -422,6 +434,7 @@ body: |
; CHECK-NEXT: [[INT:%[0-9]+]]:_(<4 x s16>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[CTPOP]](<8 x s8>)
; CHECK-NEXT: $d0 = COPY [[INT]](<4 x s16>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
+ ;
; CHECK-CSSC-LABEL: name: custom_4x16
; CHECK-CSSC: liveins: $d0
; CHECK-CSSC-NEXT: {{ $}}
@@ -454,6 +467,7 @@ body: |
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(<2 x s32>) = G_INTRINSIC intrinsic(@llvm.aarch64.neon.uaddlp), [[INT]](<4 x s16>)
; CHECK-NEXT: $d0 = COPY [[INT1]](<2 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $d0
+ ;
; CHECK-CSSC-LABEL: name: custom_2x32
; CHECK-CSSC: liveins: $d0
; CHECK-CSSC-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
index d398965817d1fd..8275ed81d3e1ff 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-ext.mir
@@ -6,54 +6,54 @@ body: |
bb.0.entry:
; CHECK-LABEL: name: test_ext
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC]](s32)
- ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC1]](s32)
- ; CHECK: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC2]](s32)
- ; CHECK: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC3]](s32)
- ; CHECK: $x0 = COPY [[COPY]](s64)
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
- ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
- ; CHECK: $x0 = COPY [[AND]](s64)
- ; CHECK: $x0 = COPY [[COPY]](s64)
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
- ; CHECK: $x0 = COPY [[SEXT_INREG]](s64)
- ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC4]], 1
- ; CHECK: $w0 = COPY [[SEXT_INREG1]](s32)
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
- ; CHECK: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C1]]
- ; CHECK: $w0 = COPY [[AND1]](s32)
- ; CHECK: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC6]](s32)
- ; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C2]]
- ; CHECK: $w0 = COPY [[AND2]](s32)
- ; CHECK: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC8]](s32)
- ; CHECK: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC9]], 16
- ; CHECK: $w0 = COPY [[SEXT_INREG2]](s32)
- ; CHECK: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C2]]
- ; CHECK: $w0 = COPY [[AND3]](s32)
- ; CHECK: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC11]](s32)
- ; CHECK: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK: $w0 = COPY [[TRUNC12]](s32)
- ; CHECK: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
- ; CHECK: $x0 = COPY [[FPEXT]](s64)
- ; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
- ; CHECK: $w0 = COPY [[COPY1]](s32)
- ; CHECK: $w0 = COPY [[C3]](s32)
- ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
- ; CHECK: $w0 = COPY [[DEF]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC]](s32)
+ ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC1]](s32)
+ ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC2]](s32)
+ ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC3]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 255
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: $x0 = COPY [[AND]](s64)
+ ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32
+ ; CHECK-NEXT: $x0 = COPY [[SEXT_INREG]](s64)
+ ; CHECK-NEXT: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC4]], 1
+ ; CHECK-NEXT: $w0 = COPY [[SEXT_INREG1]](s32)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
+ ; CHECK-NEXT: [[TRUNC5:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC5]], [[C1]]
+ ; CHECK-NEXT: $w0 = COPY [[AND1]](s32)
+ ; CHECK-NEXT: [[TRUNC6:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC6]](s32)
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[TRUNC7:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s32) = G_AND [[TRUNC7]], [[C2]]
+ ; CHECK-NEXT: $w0 = COPY [[AND2]](s32)
+ ; CHECK-NEXT: [[TRUNC8:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC8]](s32)
+ ; CHECK-NEXT: [[TRUNC9:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[SEXT_INREG2:%[0-9]+]]:_(s32) = G_SEXT_INREG [[TRUNC9]], 16
+ ; CHECK-NEXT: $w0 = COPY [[SEXT_INREG2]](s32)
+ ; CHECK-NEXT: [[TRUNC10:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[TRUNC10]], [[C2]]
+ ; CHECK-NEXT: $w0 = COPY [[AND3]](s32)
+ ; CHECK-NEXT: [[TRUNC11:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC11]](s32)
+ ; CHECK-NEXT: [[TRUNC12:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
+ ; CHECK-NEXT: $w0 = COPY [[TRUNC12]](s32)
+ ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s64) = G_FPEXT [[TRUNC12]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[FPEXT]](s64)
+ ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[COPY1]](s32)
+ ; CHECK-NEXT: $w0 = COPY [[C3]](s32)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
%0:_(s64) = COPY $x0
%1:_(s1) = G_TRUNC %0(s64)
%19:_(s32) = G_ANYEXT %1(s1)
@@ -112,8 +112,10 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_anyext_anyext
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: $w0 = COPY [[COPY]](s32)
+ ; CHECK: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
%2:_(s8) = G_ANYEXT %1(s1)
@@ -128,9 +130,11 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_anyext_sext
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
- ; CHECK: $w0 = COPY [[SEXT_INREG]](s32)
+ ; CHECK: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[COPY]], 1
+ ; CHECK-NEXT: $w0 = COPY [[SEXT_INREG]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
%2:_(s8) = G_SEXT %1(s1)
@@ -145,10 +149,12 @@ body: |
liveins: $w0
; CHECK-LABEL: name: test_anyext_zext
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: $w0 = COPY [[AND]](s32)
+ ; CHECK: liveins: $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
%0:_(s32) = COPY $w0
%1:_(s1) = G_TRUNC %0(s32)
%2:_(s8) = G_ZEXT %1(s1)
@@ -166,10 +172,11 @@ body: |
liveins: $d0
; CHECK-LABEL: name: test_zext_v8s16_from_v8s8
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
- ; CHECK: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
- ; CHECK: $q0 = COPY [[ZEXT]](<8 x s16>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:fpr(<8 x s8>) = COPY $d0
%2:_(<8 x s16>) = G_ZEXT %1(<8 x s8>)
$q0 = COPY %2(<8 x s16>)
@@ -186,10 +193,11 @@ body: |
liveins: $d0
; CHECK-LABEL: name: test_sext_v8s16_from_v8s8
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
- ; CHECK: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
- ; CHECK: $q0 = COPY [[SEXT]](<8 x s16>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:fpr(<8 x s8>) = COPY $d0
%2:_(<8 x s16>) = G_SEXT %1(<8 x s8>)
$q0 = COPY %2(<8 x s16>)
@@ -206,10 +214,11 @@ body: |
liveins: $d0
; CHECK-LABEL: name: test_anyext_v8s16_from_v8s8
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
- ; CHECK: $q0 = COPY [[ANYEXT]](<8 x s16>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<8 x s16>) = G_ANYEXT [[COPY]](<8 x s8>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%1:fpr(<8 x s8>) = COPY $d0
%2:_(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
$q0 = COPY %2(<8 x s16>)
@@ -227,10 +236,11 @@ body: |
; CHECK-LABEL: name: test_zext_v4s32_from_v4s16
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
- ; CHECK: $q0 = COPY [[ZEXT]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<4 x s32>) = G_ZEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s32>) = G_ZEXT %0(<4 x s16>)
$q0 = COPY %1(<4 x s32>)
@@ -248,10 +258,11 @@ body: |
; CHECK-LABEL: name: test_sext_v4s32_from_v4s16
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
- ; CHECK: $q0 = COPY [[SEXT]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<4 x s32>) = G_SEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s32>) = G_SEXT %0(<4 x s16>)
$q0 = COPY %1(<4 x s32>)
@@ -269,10 +280,11 @@ body: |
; CHECK-LABEL: name: test_anyext_v4s32_from_v4s16
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
- ; CHECK: $q0 = COPY [[ANYEXT]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<4 x s32>) = G_ANYEXT [[COPY]](<4 x s16>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s32>) = G_ANYEXT %0(<4 x s16>)
$q0 = COPY %1(<4 x s32>)
@@ -293,10 +305,11 @@ body: |
; CHECK-LABEL: name: test_zext_v2s64_from_v2s32
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
- ; CHECK: $q0 = COPY [[ZEXT]](<2 x s64>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s64>) = G_ZEXT %0(<2 x s32>)
$q0 = COPY %1(<2 x s64>)
@@ -317,10 +330,11 @@ body: |
; CHECK-LABEL: name: test_sext_v2s64_from_v2s32
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
- ; CHECK: $q0 = COPY [[SEXT]](<2 x s64>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<2 x s64>) = G_SEXT [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[SEXT]](<2 x s64>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s64>) = G_SEXT %0(<2 x s32>)
$q0 = COPY %1(<2 x s64>)
@@ -341,10 +355,11 @@ body: |
; CHECK-LABEL: name: test_anyext_v2s64_from_v2s32
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
- ; CHECK: $q0 = COPY [[ANYEXT]](<2 x s64>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[COPY]](<2 x s32>)
+ ; CHECK-NEXT: $q0 = COPY [[ANYEXT]](<2 x s64>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s64>) = G_ANYEXT %0(<2 x s32>)
$q0 = COPY %1(<2 x s64>)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
index 323d18ffcb59df..6e399d8a388350 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
@@ -7,15 +7,15 @@ body: |
bb.0:
; CHECK-LABEL: name: test_merge_s4
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
- ; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
- ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]]
- ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
- ; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s64)
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
- ; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
- ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
- ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
- ; CHECK: $x0 = COPY [[ANYEXT]](s64)
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[C1]], [[C]]
+ ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
+ ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s64)
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[C1]](s32)
+ ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[C]]
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND1]], [[SHL]]
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[OR]](s32)
+ ; CHECK-NEXT: $x0 = COPY [[ANYEXT]](s64)
%0:_(s64) = G_CONSTANT i64 0
%1:_(s4) = G_TRUNC %0
@@ -32,12 +32,12 @@ body: |
; This isn't legal but we don't support widening the destination type.
; CHECK-LABEL: name: test_merge_s16_s8
; CHECK: %a:_(s32) = COPY $w0
- ; CHECK: %b:_(s32) = COPY $w1
- ; CHECK: %a_t:_(s8) = G_TRUNC %a(s32)
- ; CHECK: %b_t:_(s8) = G_TRUNC %b(s32)
- ; CHECK: %m:_(s16) = G_MERGE_VALUES %a_t(s8), %b_t(s8)
- ; CHECK: %ext:_(s64) = G_ANYEXT %m(s16)
- ; CHECK: $x0 = COPY %ext(s64)
+ ; CHECK-NEXT: %b:_(s32) = COPY $w1
+ ; CHECK-NEXT: %a_t:_(s8) = G_TRUNC %a(s32)
+ ; CHECK-NEXT: %b_t:_(s8) = G_TRUNC %b(s32)
+ ; CHECK-NEXT: %m:_(s16) = G_MERGE_VALUES %a_t(s8), %b_t(s8)
+ ; CHECK-NEXT: %ext:_(s64) = G_ANYEXT %m(s16)
+ ; CHECK-NEXT: $x0 = COPY %ext(s64)
%a:_(s32) = COPY $w0
%b:_(s32) = COPY $w1
%a_t:_(s8) = G_TRUNC %a
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
index f988c6ffff9e8f..2513eb4989a5e8 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
@@ -171,7 +171,9 @@ body: |
liveins: $q0, $q1
; CHECK-LABEL: name: vector_mul_scalarize
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY1]](<2 x s64>)
@@ -540,15 +542,15 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
- ; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
- ; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)
; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s16>) = G_MUL [[BUILD_VECTOR]], [[BUILD_VECTOR]]
- ; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[MUL]](<4 x s16>)
- ; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
- ; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[MUL]](<4 x s16>)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
+ ; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)
; CHECK-NEXT: RET_ReallyLR implicit $b0
%1:_(s8) = COPY $b0
%2:_(s8) = COPY $b1
diff --git a/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll b/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
index 7e8efb64361e56..6a13d950d3b14b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-subvector-extend.ll
@@ -1,15 +1,33 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECKDAG
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* 2>&1 | FileCheck %s --check-prefixes=CHECK,FALLBACK
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; Test efficient codegen of vector extends up from legal type to 128 bit
; and 256 bit vector types.
+; CHECK-GI: warning: Instruction selection used fallback path for func3
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for func4
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for afunc3
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for afunc4
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for bfunc1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for bfunc2
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for zfunc1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for zfunc2
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for bfunc3
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for cfunc4
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for zext_v4i8_to_v4i64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sext_v4i8_to_v4i64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for zext_v8i8_to_v8i64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sext_v8i8_to_v8i64
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for zext_v32i1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sext_v32i1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for zext_v64i1
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sext_v64i1
+
;-----
; Vectors of i16.
;-----
-; FALLBACK-NOT: remark:{{.*}}(in function: func1)
define <8 x i16> @func1(<8 x i8> %v0) nounwind {
; CHECK-LABEL: func1:
; CHECK: // %bb.0:
@@ -19,7 +37,6 @@ define <8 x i16> @func1(<8 x i8> %v0) nounwind {
ret <8 x i16> %r
}
-; FALLBACK-NOT: remark:{{.*}}(in function: func2)
define <8 x i16> @func2(<8 x i8> %v0) nounwind {
; CHECK-LABEL: func2:
; CHECK: // %bb.0:
@@ -53,7 +70,6 @@ define <16 x i16> @func4(<16 x i8> %v0) nounwind {
; Vectors of i32.
;-----
-; FALLBACK-NOT: remark:{{.*}}(in function: afunc1)
define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
; CHECK-LABEL: afunc1:
; CHECK: // %bb.0:
@@ -63,7 +79,6 @@ define <4 x i32> @afunc1(<4 x i16> %v0) nounwind {
ret <4 x i32> %r
}
-; FALLBACK-NOT: remark:{{.*}}(in function: afunc2)
define <4 x i32> @afunc2(<4 x i16> %v0) nounwind {
; CHECK-LABEL: afunc2:
; CHECK: // %bb.0:
@@ -632,23 +647,23 @@ define <64 x i8> @sext_v64i1(<64 x i1> %arg) {
ret <64 x i8> %res
}
+; X0 & X1 are the real return registers, SDAG messes with v0 too for unknown reasons.
define <1 x i128> @sext_v1x64(<1 x i64> %arg) {
- ; X0 & X1 are the real return registers, SDAG messes with v0 too for unknown reasons.
-; CHECKDAG-LABEL: sext_v1x64:
-; CHECKDAG: // %bb.0:
-; CHECKDAG-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECKDAG-NEXT: fmov x8, d0
-; CHECKDAG-NEXT: asr x1, x8, #63
-; CHECKDAG-NEXT: mov.d v0[1], x1
-; CHECKDAG-NEXT: fmov x0, d0
-; CHECKDAG-NEXT: ret
+; CHECK-SD-LABEL: sext_v1x64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: fmov x8, d0
+; CHECK-SD-NEXT: asr x1, x8, #63
+; CHECK-SD-NEXT: mov.d v0[1], x1
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; FALLBACK-LABEL: sext_v1x64:
-; FALLBACK: // %bb.0:
-; FALLBACK-NEXT: fmov x8, d0
-; FALLBACK-NEXT: fmov x0, d0
-; FALLBACK-NEXT: asr x1, x8, #63
-; FALLBACK-NEXT: ret
+; CHECK-GI-LABEL: sext_v1x64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: asr x1, x8, #63
+; CHECK-GI-NEXT: ret
%res = sext <1 x i64> %arg to <1 x i128>
ret <1 x i128> %res
}
diff --git a/llvm/test/CodeGen/AArch64/arm64-vabs.ll b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
index 30599595bfbb00..08cb1ef2e0b51e 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vabs.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vabs.ll
@@ -1,8 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,DAG %s
-; RUN: llc < %s -global-isel -global-isel-abort=2 -pass-remarks-missed=gisel* -mtriple=arm64-eabi -aarch64-neon-syntax=apple 2>&1 | FileCheck %s --check-prefixes=CHECK,GISEL,FALLBACK
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck -check-prefixes=CHECK,CHECK-SD %s
+; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for uabd16b_rdx
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uabd16b_rdx_i32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sabd16b_rdx_i32
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uabd8h_rdx
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sabd8h_rdx
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uabd4s_rdx
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for sabd4s_rdx
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_8b
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_16b
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_4h
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_8h
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_2s
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_4s
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_1d
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for abs_1d_honestly
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabds
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for fabdd
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for uabd_i64
-; FALLBACK-NOT: remark:{{.*}} sabdl8h
define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl8h:
; CHECK: // %bb.0:
@@ -17,7 +35,6 @@ define <8 x i16> @sabdl8h(ptr %A, ptr %B) nounwind {
ret <8 x i16> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} sabdl4s
define <4 x i32> @sabdl4s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl4s:
; CHECK: // %bb.0:
@@ -32,7 +49,6 @@ define <4 x i32> @sabdl4s(ptr %A, ptr %B) nounwind {
ret <4 x i32> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} sabdl2d
define <2 x i64> @sabdl2d(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: sabdl2d:
; CHECK: // %bb.0:
@@ -47,23 +63,22 @@ define <2 x i64> @sabdl2d(ptr %A, ptr %B) nounwind {
ret <2 x i64> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} sabdl2_8h
define <8 x i16> @sabdl2_8h(ptr %A, ptr %B) nounwind {
-; DAG-LABEL: sabdl2_8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d0, [x0, #8]
-; DAG-NEXT: ldr d1, [x1, #8]
-; DAG-NEXT: sabdl.8h v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabdl2_8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0, #8]
+; CHECK-SD-NEXT: ldr d1, [x1, #8]
+; CHECK-SD-NEXT: sabdl.8h v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabdl2_8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: sabdl.8h v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabdl2_8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: sabdl.8h v0, v0, v1
+; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
%load2 = load <16 x i8>, ptr %B
%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -73,23 +88,22 @@ define <8 x i16> @sabdl2_8h(ptr %A, ptr %B) nounwind {
ret <8 x i16> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} sabdl2_4s
define <4 x i32> @sabdl2_4s(ptr %A, ptr %B) nounwind {
-; DAG-LABEL: sabdl2_4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d0, [x0, #8]
-; DAG-NEXT: ldr d1, [x1, #8]
-; DAG-NEXT: sabdl.4s v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabdl2_4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0, #8]
+; CHECK-SD-NEXT: ldr d1, [x1, #8]
+; CHECK-SD-NEXT: sabdl.4s v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabdl2_4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: sabdl.4s v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabdl2_4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: sabdl.4s v0, v0, v1
+; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
%load2 = load <8 x i16>, ptr %B
%tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -99,23 +113,22 @@ define <4 x i32> @sabdl2_4s(ptr %A, ptr %B) nounwind {
ret <4 x i32> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} sabdl2_2d
define <2 x i64> @sabdl2_2d(ptr %A, ptr %B) nounwind {
-; DAG-LABEL: sabdl2_2d:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d0, [x0, #8]
-; DAG-NEXT: ldr d1, [x1, #8]
-; DAG-NEXT: sabdl.2d v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabdl2_2d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0, #8]
+; CHECK-SD-NEXT: ldr d1, [x1, #8]
+; CHECK-SD-NEXT: sabdl.2d v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabdl2_2d:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: sabdl.2d v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabdl2_2d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: sabdl.2d v0, v0, v1
+; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
%load2 = load <4 x i32>, ptr %B
%tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -125,7 +138,6 @@ define <2 x i64> @sabdl2_2d(ptr %A, ptr %B) nounwind {
ret <2 x i64> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} uabdl8h)
define <8 x i16> @uabdl8h(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabdl8h:
; CHECK: // %bb.0:
@@ -140,7 +152,6 @@ define <8 x i16> @uabdl8h(ptr %A, ptr %B) nounwind {
ret <8 x i16> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} uabdl4s)
define <4 x i32> @uabdl4s(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabdl4s:
; CHECK: // %bb.0:
@@ -155,7 +166,6 @@ define <4 x i32> @uabdl4s(ptr %A, ptr %B) nounwind {
ret <4 x i32> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} uabdl2d)
define <2 x i64> @uabdl2d(ptr %A, ptr %B) nounwind {
; CHECK-LABEL: uabdl2d:
; CHECK: // %bb.0:
@@ -170,23 +180,22 @@ define <2 x i64> @uabdl2d(ptr %A, ptr %B) nounwind {
ret <2 x i64> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} uabdl2_8h
define <8 x i16> @uabdl2_8h(ptr %A, ptr %B) nounwind {
-; DAG-LABEL: uabdl2_8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d0, [x0, #8]
-; DAG-NEXT: ldr d1, [x1, #8]
-; DAG-NEXT: uabdl.8h v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabdl2_8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0, #8]
+; CHECK-SD-NEXT: ldr d1, [x1, #8]
+; CHECK-SD-NEXT: uabdl.8h v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabdl2_8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: uabdl.8h v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabdl2_8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: uabdl.8h v0, v0, v1
+; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
%load2 = load <16 x i8>, ptr %B
%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
@@ -197,23 +206,22 @@ define <8 x i16> @uabdl2_8h(ptr %A, ptr %B) nounwind {
ret <8 x i16> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} uabdl2_4s
define <4 x i32> @uabdl2_4s(ptr %A, ptr %B) nounwind {
-; DAG-LABEL: uabdl2_4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d0, [x0, #8]
-; DAG-NEXT: ldr d1, [x1, #8]
-; DAG-NEXT: uabdl.4s v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabdl2_4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0, #8]
+; CHECK-SD-NEXT: ldr d1, [x1, #8]
+; CHECK-SD-NEXT: uabdl.4s v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabdl2_4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: uabdl.4s v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabdl2_4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: uabdl.4s v0, v0, v1
+; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
%load2 = load <8 x i16>, ptr %B
%tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
@@ -223,23 +231,22 @@ define <4 x i32> @uabdl2_4s(ptr %A, ptr %B) nounwind {
ret <4 x i32> %tmp4
}
-; FALLBACK-NOT: remark:{{.*}} uabdl2_2d
define <2 x i64> @uabdl2_2d(ptr %A, ptr %B) nounwind {
-; DAG-LABEL: uabdl2_2d:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d0, [x0, #8]
-; DAG-NEXT: ldr d1, [x1, #8]
-; DAG-NEXT: uabdl.2d v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabdl2_2d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0, #8]
+; CHECK-SD-NEXT: ldr d1, [x1, #8]
+; CHECK-SD-NEXT: uabdl.2d v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabdl2_2d:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: uabdl.2d v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabdl2_2d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: uabdl.2d v0, v0, v1
+; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
%load2 = load <4 x i32>, ptr %B
%tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
@@ -352,28 +359,26 @@ define i32 @sabd8h_rdx(<8 x i16> %a, <8 x i16> %b) {
}
define i32 @uabdl4s_rdx_i32(<4 x i16> %a, <4 x i16> %b) {
-; DAG-LABEL: uabdl4s_rdx_i32:
-; DAG: // %bb.0:
-; DAG-NEXT: uabdl.4s v0, v0, v1
-; DAG-NEXT: addv.4s s0, v0
-; DAG-NEXT: fmov w0, s0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabdl4s_rdx_i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uabdl.4s v0, v0, v1
+; CHECK-SD-NEXT: addv.4s s0, v0
+; CHECK-SD-NEXT: fmov w0, s0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabdl4s_rdx_i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v2, #0000000000000000
-; GISEL-NEXT: usubl.4s v0, v0, v1
-; GISEL-NEXT: cmgt.4s v1, v2, v0
-; GISEL-NEXT: neg.4s v2, v0
-; GISEL-NEXT: bit.16b v0, v2, v1
-; GISEL-NEXT: addv.4s s0, v0
-; GISEL-NEXT: fmov w0, s0
-; GISEL-NEXT: ret
-
-; GISel doesn't match this pattern yet.
+; CHECK-GI-LABEL: uabdl4s_rdx_i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
+; CHECK-GI-NEXT: usubl.4s v0, v0, v1
+; CHECK-GI-NEXT: cmgt.4s v1, v2, v0
+; CHECK-GI-NEXT: neg.4s v2, v0
+; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: addv.4s s0, v0
+; CHECK-GI-NEXT: fmov w0, s0
+; CHECK-GI-NEXT: ret
%aext = zext <4 x i16> %a to <4 x i32>
%bext = zext <4 x i16> %b to <4 x i32>
- %ab
diff = sub nsw <4 x i32> %aext, %bext
+ %ab
diff = sub nsw <4 x i32> %aext, %bext
%abcmp = icmp slt <4 x i32> %ab
diff , zeroinitializer
%ababs = sub nsw <4 x i32> zeroinitializer, %ab
diff
%absel = select <4 x i1> %abcmp, <4 x i32> %ababs, <4 x i32> %ab
diff
@@ -423,25 +428,23 @@ define i64 @sabd4s_rdx(<4 x i32> %a, <4 x i32> %b) {
}
define i64 @uabdl2d_rdx_i64(<2 x i32> %a, <2 x i32> %b) {
-; DAG-LABEL: uabdl2d_rdx_i64:
-; DAG: // %bb.0:
-; DAG-NEXT: uabdl.2d v0, v0, v1
-; DAG-NEXT: addp.2d d0, v0
-; DAG-NEXT: fmov x0, d0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabdl2d_rdx_i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uabdl.2d v0, v0, v1
+; CHECK-SD-NEXT: addp.2d d0, v0
+; CHECK-SD-NEXT: fmov x0, d0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabdl2d_rdx_i64:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v2, #0000000000000000
-; GISEL-NEXT: usubl.2d v0, v0, v1
-; GISEL-NEXT: cmgt.2d v1, v2, v0
-; GISEL-NEXT: neg.2d v2, v0
-; GISEL-NEXT: bit.16b v0, v2, v1
-; GISEL-NEXT: addp.2d d0, v0
-; GISEL-NEXT: fmov x0, d0
-; GISEL-NEXT: ret
-
-; GISel doesn't match this pattern yet
+; CHECK-GI-LABEL: uabdl2d_rdx_i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
+; CHECK-GI-NEXT: usubl.2d v0, v0, v1
+; CHECK-GI-NEXT: cmgt.2d v1, v2, v0
+; CHECK-GI-NEXT: neg.2d v2, v0
+; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: addp.2d d0, v0
+; CHECK-GI-NEXT: fmov x0, d0
+; CHECK-GI-NEXT: ret
%aext = zext <2 x i32> %a to <2 x i64>
%bext = zext <2 x i32> %b to <2 x i64>
%ab
diff = sub nsw <2 x i64> %aext, %bext
@@ -952,23 +955,22 @@ declare <4 x i32> @llvm.aarch64.neon.abs.v4i32(<4 x i32>) nounwind readnone
declare <1 x i64> @llvm.aarch64.neon.abs.v1i64(<1 x i64>) nounwind readnone
declare i64 @llvm.aarch64.neon.abs.i64(i64) nounwind readnone
-; FALLBACK-NOT: remark:{{.*}} sabal8h
define <8 x i16> @sabal8h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: sabal8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: sabal.8h v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabal8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: sabal.8h v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabal8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: sabal.8h v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabal8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: sabal.8h v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = load <8 x i8>, ptr %B
%tmp3 = load <8 x i16>, ptr %C
@@ -978,23 +980,22 @@ define <8 x i16> @sabal8h(ptr %A, ptr %B, ptr %C) nounwind {
ret <8 x i16> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} sabal4s
define <4 x i32> @sabal4s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: sabal4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: sabal.4s v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabal4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: sabal.4s v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabal4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: sabal.4s v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabal4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: sabal.4s v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = load <4 x i16>, ptr %B
%tmp3 = load <4 x i32>, ptr %C
@@ -1004,23 +1005,22 @@ define <4 x i32> @sabal4s(ptr %A, ptr %B, ptr %C) nounwind {
ret <4 x i32> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} sabal2d
define <2 x i64> @sabal2d(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: sabal2d:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: sabal.2d v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabal2d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: sabal.2d v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabal2d:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: sabal.2d v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabal2d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: sabal.2d v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = load <2 x i32>, ptr %B
%tmp3 = load <2 x i64>, ptr %C
@@ -1031,25 +1031,24 @@ define <2 x i64> @sabal2d(ptr %A, ptr %B, ptr %C) nounwind {
ret <2 x i64> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} sabal2_8h
define <8 x i16> @sabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: sabal2_8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: ldr d1, [x0, #8]
-; DAG-NEXT: ldr d2, [x1, #8]
-; DAG-NEXT: sabal.8h v0, v1, v2
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabal2_8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: ldr d1, [x0, #8]
+; CHECK-SD-NEXT: ldr d2, [x1, #8]
+; CHECK-SD-NEXT: sabal.8h v0, v1, v2
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabal2_8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v2, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: sabal.8h v0, v2, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabal2_8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v2, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: sabal.8h v0, v2, v1
+; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
%load2 = load <16 x i8>, ptr %B
%tmp3 = load <8 x i16>, ptr %C
@@ -1061,25 +1060,24 @@ define <8 x i16> @sabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {
ret <8 x i16> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} sabal2_4s
define <4 x i32> @sabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: sabal2_4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: ldr d1, [x0, #8]
-; DAG-NEXT: ldr d2, [x1, #8]
-; DAG-NEXT: sabal.4s v0, v1, v2
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabal2_4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: ldr d1, [x0, #8]
+; CHECK-SD-NEXT: ldr d2, [x1, #8]
+; CHECK-SD-NEXT: sabal.4s v0, v1, v2
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabal2_4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v2, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: sabal.4s v0, v2, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabal2_4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v2, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: sabal.4s v0, v2, v1
+; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
%load2 = load <8 x i16>, ptr %B
%tmp3 = load <4 x i32>, ptr %C
@@ -1091,25 +1089,24 @@ define <4 x i32> @sabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {
ret <4 x i32> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} sabal2_2d
define <2 x i64> @sabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: sabal2_2d:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: ldr d1, [x0, #8]
-; DAG-NEXT: ldr d2, [x1, #8]
-; DAG-NEXT: sabal.2d v0, v1, v2
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabal2_2d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: ldr d1, [x0, #8]
+; CHECK-SD-NEXT: ldr d2, [x1, #8]
+; CHECK-SD-NEXT: sabal.2d v0, v1, v2
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabal2_2d:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v2, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: sabal.2d v0, v2, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabal2_2d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v2, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: sabal.2d v0, v2, v1
+; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
%load2 = load <4 x i32>, ptr %B
%tmp3 = load <2 x i64>, ptr %C
@@ -1121,23 +1118,22 @@ define <2 x i64> @sabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {
ret <2 x i64> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} uabal8h
define <8 x i16> @uabal8h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uabal8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: uabal.8h v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabal8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: uabal.8h v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabal8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uabal.8h v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabal8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uabal.8h v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = load <8 x i8>, ptr %B
%tmp3 = load <8 x i16>, ptr %C
@@ -1147,23 +1143,22 @@ define <8 x i16> @uabal8h(ptr %A, ptr %B, ptr %C) nounwind {
ret <8 x i16> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} uabal8s
define <4 x i32> @uabal4s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uabal4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: uabal.4s v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabal4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: uabal.4s v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabal4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uabal.4s v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabal4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uabal.4s v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = load <4 x i16>, ptr %B
%tmp3 = load <4 x i32>, ptr %C
@@ -1173,23 +1168,22 @@ define <4 x i32> @uabal4s(ptr %A, ptr %B, ptr %C) nounwind {
ret <4 x i32> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} uabal2d
define <2 x i64> @uabal2d(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uabal2d:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: uabal.2d v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabal2d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: uabal.2d v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabal2d:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uabal.2d v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabal2d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uabal.2d v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = load <2 x i32>, ptr %B
%tmp3 = load <2 x i64>, ptr %C
@@ -1199,25 +1193,24 @@ define <2 x i64> @uabal2d(ptr %A, ptr %B, ptr %C) nounwind {
ret <2 x i64> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} uabal2_8h
define <8 x i16> @uabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uabal2_8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: ldr d1, [x0, #8]
-; DAG-NEXT: ldr d2, [x1, #8]
-; DAG-NEXT: uabal.8h v0, v1, v2
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabal2_8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: ldr d1, [x0, #8]
+; CHECK-SD-NEXT: ldr d2, [x1, #8]
+; CHECK-SD-NEXT: uabal.8h v0, v1, v2
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabal2_8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v2, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uabal.8h v0, v2, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabal2_8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v2, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uabal.8h v0, v2, v1
+; CHECK-GI-NEXT: ret
%load1 = load <16 x i8>, ptr %A
%load2 = load <16 x i8>, ptr %B
%tmp3 = load <8 x i16>, ptr %C
@@ -1229,25 +1222,24 @@ define <8 x i16> @uabal2_8h(ptr %A, ptr %B, ptr %C) nounwind {
ret <8 x i16> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} uabal2_4s
define <4 x i32> @uabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uabal2_4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: ldr d1, [x0, #8]
-; DAG-NEXT: ldr d2, [x1, #8]
-; DAG-NEXT: uabal.4s v0, v1, v2
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabal2_4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: ldr d1, [x0, #8]
+; CHECK-SD-NEXT: ldr d2, [x1, #8]
+; CHECK-SD-NEXT: uabal.4s v0, v1, v2
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabal2_4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v2, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uabal.4s v0, v2, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabal2_4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v2, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uabal.4s v0, v2, v1
+; CHECK-GI-NEXT: ret
%load1 = load <8 x i16>, ptr %A
%load2 = load <8 x i16>, ptr %B
%tmp3 = load <4 x i32>, ptr %C
@@ -1259,25 +1251,24 @@ define <4 x i32> @uabal2_4s(ptr %A, ptr %B, ptr %C) nounwind {
ret <4 x i32> %tmp5
}
-; FALLBACK-NOT: remark:{{.*}} uabal2_2d
define <2 x i64> @uabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uabal2_2d:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: ldr d1, [x0, #8]
-; DAG-NEXT: ldr d2, [x1, #8]
-; DAG-NEXT: uabal.2d v0, v1, v2
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabal2_2d:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: ldr d1, [x0, #8]
+; CHECK-SD-NEXT: ldr d2, [x1, #8]
+; CHECK-SD-NEXT: uabal.2d v0, v1, v2
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabal2_2d:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q0, [x0]
-; GISEL-NEXT: ldr q1, [x1]
-; GISEL-NEXT: ext.16b v2, v0, v0, #8
-; GISEL-NEXT: ext.16b v1, v1, v0, #8
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uabal.2d v0, v2, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabal2_2d:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ldr q1, [x1]
+; CHECK-GI-NEXT: ext.16b v2, v0, v0, #8
+; CHECK-GI-NEXT: ext.16b v1, v1, v0, #8
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uabal.2d v0, v2, v1
+; CHECK-GI-NEXT: ret
%load1 = load <4 x i32>, ptr %A
%load2 = load <4 x i32>, ptr %B
%tmp3 = load <2 x i64>, ptr %C
@@ -1290,21 +1281,21 @@ define <2 x i64> @uabal2_2d(ptr %A, ptr %B, ptr %C) nounwind {
}
define <8 x i8> @saba_8b(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: saba_8b:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr d0, [x2]
-; DAG-NEXT: saba.8b v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: saba_8b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr d0, [x2]
+; CHECK-SD-NEXT: saba.8b v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: saba_8b:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr d0, [x2]
-; GISEL-NEXT: saba.8b v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: saba_8b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr d0, [x2]
+; CHECK-GI-NEXT: saba.8b v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -1314,21 +1305,21 @@ define <8 x i8> @saba_8b(ptr %A, ptr %B, ptr %C) nounwind {
}
define <16 x i8> @saba_16b(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: saba_16b:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q1, [x1]
-; DAG-NEXT: ldr q2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: saba.16b v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: saba_16b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q1, [x1]
+; CHECK-SD-NEXT: ldr q2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: saba.16b v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: saba_16b:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q1, [x0]
-; GISEL-NEXT: ldr q2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: saba.16b v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: saba_16b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q1, [x0]
+; CHECK-GI-NEXT: ldr q2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: saba.16b v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <16 x i8>, ptr %A
%tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
@@ -1338,21 +1329,21 @@ define <16 x i8> @saba_16b(ptr %A, ptr %B, ptr %C) nounwind {
}
define <4 x i16> @saba_4h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: saba_4h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr d0, [x2]
-; DAG-NEXT: saba.4h v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: saba_4h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr d0, [x2]
+; CHECK-SD-NEXT: saba.4h v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: saba_4h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr d0, [x2]
-; GISEL-NEXT: saba.4h v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: saba_4h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr d0, [x2]
+; CHECK-GI-NEXT: saba.4h v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.aarch64.neon.sabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -1362,21 +1353,21 @@ define <4 x i16> @saba_4h(ptr %A, ptr %B, ptr %C) nounwind {
}
define <8 x i16> @saba_8h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: saba_8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q1, [x1]
-; DAG-NEXT: ldr q2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: saba.8h v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: saba_8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q1, [x1]
+; CHECK-SD-NEXT: ldr q2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: saba.8h v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: saba_8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q1, [x0]
-; GISEL-NEXT: ldr q2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: saba.8h v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: saba_8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q1, [x0]
+; CHECK-GI-NEXT: ldr q2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: saba.8h v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
@@ -1386,21 +1377,21 @@ define <8 x i16> @saba_8h(ptr %A, ptr %B, ptr %C) nounwind {
}
define <2 x i32> @saba_2s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: saba_2s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr d0, [x2]
-; DAG-NEXT: saba.2s v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: saba_2s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr d0, [x2]
+; CHECK-SD-NEXT: saba.2s v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: saba_2s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr d0, [x2]
-; GISEL-NEXT: saba.2s v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: saba_2s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr d0, [x2]
+; CHECK-GI-NEXT: saba.2s v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -1410,21 +1401,21 @@ define <2 x i32> @saba_2s(ptr %A, ptr %B, ptr %C) nounwind {
}
define <4 x i32> @saba_4s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: saba_4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q1, [x1]
-; DAG-NEXT: ldr q2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: saba.4s v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: saba_4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q1, [x1]
+; CHECK-SD-NEXT: ldr q2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: saba.4s v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: saba_4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q1, [x0]
-; GISEL-NEXT: ldr q2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: saba.4s v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: saba_4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q1, [x0]
+; CHECK-GI-NEXT: ldr q2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: saba.4s v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.aarch64.neon.sabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
@@ -1434,21 +1425,21 @@ define <4 x i32> @saba_4s(ptr %A, ptr %B, ptr %C) nounwind {
}
define <8 x i8> @uaba_8b(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uaba_8b:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr d0, [x2]
-; DAG-NEXT: uaba.8b v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uaba_8b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr d0, [x2]
+; CHECK-SD-NEXT: uaba.8b v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uaba_8b:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr d0, [x2]
-; GISEL-NEXT: uaba.8b v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uaba_8b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr d0, [x2]
+; CHECK-GI-NEXT: uaba.8b v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i8>, ptr %A
%tmp2 = load <8 x i8>, ptr %B
%tmp3 = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
@@ -1458,21 +1449,21 @@ define <8 x i8> @uaba_8b(ptr %A, ptr %B, ptr %C) nounwind {
}
define <16 x i8> @uaba_16b(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uaba_16b:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q1, [x1]
-; DAG-NEXT: ldr q2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: uaba.16b v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uaba_16b:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q1, [x1]
+; CHECK-SD-NEXT: ldr q2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: uaba.16b v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uaba_16b:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q1, [x0]
-; GISEL-NEXT: ldr q2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uaba.16b v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uaba_16b:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q1, [x0]
+; CHECK-GI-NEXT: ldr q2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uaba.16b v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <16 x i8>, ptr %A
%tmp2 = load <16 x i8>, ptr %B
%tmp3 = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
@@ -1482,21 +1473,21 @@ define <16 x i8> @uaba_16b(ptr %A, ptr %B, ptr %C) nounwind {
}
define <4 x i16> @uaba_4h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uaba_4h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr d0, [x2]
-; DAG-NEXT: uaba.4h v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uaba_4h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr d0, [x2]
+; CHECK-SD-NEXT: uaba.4h v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uaba_4h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr d0, [x2]
-; GISEL-NEXT: uaba.4h v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uaba_4h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr d0, [x2]
+; CHECK-GI-NEXT: uaba.4h v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i16>, ptr %A
%tmp2 = load <4 x i16>, ptr %B
%tmp3 = call <4 x i16> @llvm.aarch64.neon.uabd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
@@ -1506,21 +1497,21 @@ define <4 x i16> @uaba_4h(ptr %A, ptr %B, ptr %C) nounwind {
}
define <8 x i16> @uaba_8h(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uaba_8h:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q1, [x1]
-; DAG-NEXT: ldr q2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: uaba.8h v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uaba_8h:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q1, [x1]
+; CHECK-SD-NEXT: ldr q2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: uaba.8h v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uaba_8h:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q1, [x0]
-; GISEL-NEXT: ldr q2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uaba.8h v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uaba_8h:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q1, [x0]
+; CHECK-GI-NEXT: ldr q2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uaba.8h v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <8 x i16>, ptr %A
%tmp2 = load <8 x i16>, ptr %B
%tmp3 = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
@@ -1530,21 +1521,21 @@ define <8 x i16> @uaba_8h(ptr %A, ptr %B, ptr %C) nounwind {
}
define <2 x i32> @uaba_2s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uaba_2s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr d1, [x1]
-; DAG-NEXT: ldr d2, [x0]
-; DAG-NEXT: ldr d0, [x2]
-; DAG-NEXT: uaba.2s v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uaba_2s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d1, [x1]
+; CHECK-SD-NEXT: ldr d2, [x0]
+; CHECK-SD-NEXT: ldr d0, [x2]
+; CHECK-SD-NEXT: uaba.2s v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uaba_2s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr d1, [x0]
-; GISEL-NEXT: ldr d2, [x1]
-; GISEL-NEXT: ldr d0, [x2]
-; GISEL-NEXT: uaba.2s v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uaba_2s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d1, [x0]
+; CHECK-GI-NEXT: ldr d2, [x1]
+; CHECK-GI-NEXT: ldr d0, [x2]
+; CHECK-GI-NEXT: uaba.2s v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <2 x i32>, ptr %A
%tmp2 = load <2 x i32>, ptr %B
%tmp3 = call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
@@ -1554,21 +1545,21 @@ define <2 x i32> @uaba_2s(ptr %A, ptr %B, ptr %C) nounwind {
}
define <4 x i32> @uaba_4s(ptr %A, ptr %B, ptr %C) nounwind {
-; DAG-LABEL: uaba_4s:
-; DAG: // %bb.0:
-; DAG-NEXT: ldr q1, [x1]
-; DAG-NEXT: ldr q2, [x0]
-; DAG-NEXT: ldr q0, [x2]
-; DAG-NEXT: uaba.4s v0, v2, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uaba_4s:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q1, [x1]
+; CHECK-SD-NEXT: ldr q2, [x0]
+; CHECK-SD-NEXT: ldr q0, [x2]
+; CHECK-SD-NEXT: uaba.4s v0, v2, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uaba_4s:
-; GISEL: // %bb.0:
-; GISEL-NEXT: ldr q1, [x0]
-; GISEL-NEXT: ldr q2, [x1]
-; GISEL-NEXT: ldr q0, [x2]
-; GISEL-NEXT: uaba.4s v0, v1, v2
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uaba_4s:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q1, [x0]
+; CHECK-GI-NEXT: ldr q2, [x1]
+; CHECK-GI-NEXT: ldr q0, [x2]
+; CHECK-GI-NEXT: uaba.4s v0, v1, v2
+; CHECK-GI-NEXT: ret
%tmp1 = load <4 x i32>, ptr %A
%tmp2 = load <4 x i32>, ptr %B
%tmp3 = call <4 x i32> @llvm.aarch64.neon.uabd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
@@ -1622,125 +1613,123 @@ define double @fabdd_from_fsub_fabs(double %a, double %b) nounwind {
declare float @llvm.fabs.f32(float) nounwind readnone
declare double @llvm.fabs.f64(double) nounwind readnone
-; FALLBACK-NOT: remark:{{.*}} uabdl_from_extract_dup
define <2 x i64> @uabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
-; CHECK-LABEL: uabdl_from_extract_dup:
-; CHECK: // %bb.0:
-; CHECK-NEXT: dup.2s v1, w0
-; GISEL-NEXT: ext.16b v0, v0, v0, #0
-; CHECK-NEXT: uabdl.2d v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: uabdl_from_extract_dup:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: dup.2s v1, w0
+; CHECK-SD-NEXT: uabdl.2d v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: uabdl_from_extract_dup:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: dup.2s v1, w0
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #0
+; CHECK-GI-NEXT: uabdl.2d v0, v0, v1
+; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
%lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
-
%res = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
%res1 = zext <2 x i32> %res to <2 x i64>
ret <2 x i64> %res1
}
-; FALLBACK-NOT: remark:{{.*}} uabdl2_from_extract_dup
define <2 x i64> @uabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
-; DAG-LABEL: uabdl2_from_extract_dup:
-; DAG: // %bb.0:
-; DAG-NEXT: dup.4s v1, w0
-; DAG-NEXT: uabdl2.2d v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabdl2_from_extract_dup:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: dup.4s v1, w0
+; CHECK-SD-NEXT: uabdl2.2d v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabdl2_from_extract_dup:
-; GISEL: // %bb.0:
-; GISEL-NEXT: dup.2s v1, w0
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: uabdl.2d v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabdl2_from_extract_dup:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: dup.2s v1, w0
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: uabdl.2d v0, v0, v1
+; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
%lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
%res = tail call <2 x i32> @llvm.aarch64.neon.uabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
%res1 = zext <2 x i32> %res to <2 x i64>
ret <2 x i64> %res1
}
-; FALLBACK-NOT: remark:{{.*}} sabdl_from_extract_dup
define <2 x i64> @sabdl_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
-; CHECK-LABEL: sabdl_from_extract_dup:
-; CHECK: // %bb.0:
-; CHECK-NEXT: dup.2s v1, w0
-; GISEL-NEXT: ext.16b v0, v0, v0, #0
-; CHECK-NEXT: sabdl.2d v0, v0, v1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sabdl_from_extract_dup:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: dup.2s v1, w0
+; CHECK-SD-NEXT: sabdl.2d v0, v0, v1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sabdl_from_extract_dup:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: dup.2s v1, w0
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #0
+; CHECK-GI-NEXT: sabdl.2d v0, v0, v1
+; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
%lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
-
%res = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
%res1 = zext <2 x i32> %res to <2 x i64>
ret <2 x i64> %res1
}
-; FALLBACK-NOT: remark:{{.*}} sabdl2_from_extract_dup
define <2 x i64> @sabdl2_from_extract_dup(<4 x i32> %lhs, i32 %rhs) {
-; DAG-LABEL: sabdl2_from_extract_dup:
-; DAG: // %bb.0:
-; DAG-NEXT: dup.4s v1, w0
-; DAG-NEXT: sabdl2.2d v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: sabdl2_from_extract_dup:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: dup.4s v1, w0
+; CHECK-SD-NEXT: sabdl2.2d v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: sabdl2_from_extract_dup:
-; GISEL: // %bb.0:
-; GISEL-NEXT: dup.2s v1, w0
-; GISEL-NEXT: ext.16b v0, v0, v0, #8
-; GISEL-NEXT: sabdl.2d v0, v0, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: sabdl2_from_extract_dup:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: dup.2s v1, w0
+; CHECK-GI-NEXT: ext.16b v0, v0, v0, #8
+; CHECK-GI-NEXT: sabdl.2d v0, v0, v1
+; CHECK-GI-NEXT: ret
%rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 0
%rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 1
-
%lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
-
%res = tail call <2 x i32> @llvm.aarch64.neon.sabd.v2i32(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind
%res1 = zext <2 x i32> %res to <2 x i64>
ret <2 x i64> %res1
}
define <2 x i32> @abspattern1(<2 x i32> %a) nounwind {
-; DAG-LABEL: abspattern1:
-; DAG: // %bb.0:
-; DAG-NEXT: abs.2s v0, v0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: abspattern1:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: abs.2s v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: abspattern1:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v1, #0000000000000000
-; GISEL-NEXT: neg.2s v2, v0
-; GISEL-NEXT: cmge.2s v1, v0, v1
-; GISEL-NEXT: bif.8b v0, v2, v1
-; GISEL-NEXT: ret
-
+; CHECK-GI-LABEL: abspattern1:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
+; CHECK-GI-NEXT: neg.2s v2, v0
+; CHECK-GI-NEXT: cmge.2s v1, v0, v1
+; CHECK-GI-NEXT: bif.8b v0, v2, v1
+; CHECK-GI-NEXT: ret
%tmp1neg = sub <2 x i32> zeroinitializer, %a
%b = icmp sge <2 x i32> %a, zeroinitializer
%abs = select <2 x i1> %b, <2 x i32> %a, <2 x i32> %tmp1neg
ret <2 x i32> %abs
}
+; For GlobalISel, this generates terrible code until we can pattern match this to abs.
define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
-; DAG-LABEL: abspattern2:
-; DAG: // %bb.0:
-; DAG-NEXT: abs.4h v0, v0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: abspattern2:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: abs.4h v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: abspattern2:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v1, #0000000000000000
-; GISEL-NEXT: neg.4h v2, v0
-; GISEL-NEXT: cmgt.4h v1, v0, v1
-; GISEL-NEXT: bif.8b v0, v2, v1
-; GISEL-NEXT: ret
-; For GlobalISel, this generates terrible code until we can pattern match this to abs.
-
+; CHECK-GI-LABEL: abspattern2:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
+; CHECK-GI-NEXT: neg.4h v2, v0
+; CHECK-GI-NEXT: cmgt.4h v1, v0, v1
+; CHECK-GI-NEXT: bif.8b v0, v2, v1
+; CHECK-GI-NEXT: ret
%tmp1neg = sub <4 x i16> zeroinitializer, %a
%b = icmp sgt <4 x i16> %a, zeroinitializer
%abs = select <4 x i1> %b, <4 x i16> %a, <4 x i16> %tmp1neg
@@ -1748,19 +1737,18 @@ define <4 x i16> @abspattern2(<4 x i16> %a) nounwind {
}
define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
-; DAG-LABEL: abspattern3:
-; DAG: // %bb.0:
-; DAG-NEXT: abs.8b v0, v0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: abspattern3:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: abs.8b v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: abspattern3:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v1, #0000000000000000
-; GISEL-NEXT: neg.8b v2, v0
-; GISEL-NEXT: cmgt.8b v1, v1, v0
-; GISEL-NEXT: bit.8b v0, v2, v1
-; GISEL-NEXT: ret
-
+; CHECK-GI-LABEL: abspattern3:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
+; CHECK-GI-NEXT: neg.8b v2, v0
+; CHECK-GI-NEXT: cmgt.8b v1, v1, v0
+; CHECK-GI-NEXT: bit.8b v0, v2, v1
+; CHECK-GI-NEXT: ret
%tmp1neg = sub <8 x i8> zeroinitializer, %a
%b = icmp slt <8 x i8> %a, zeroinitializer
%abs = select <8 x i1> %b, <8 x i8> %tmp1neg, <8 x i8> %a
@@ -1768,19 +1756,18 @@ define <8 x i8> @abspattern3(<8 x i8> %a) nounwind {
}
define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
-; DAG-LABEL: abspattern4:
-; DAG: // %bb.0:
-; DAG-NEXT: abs.4s v0, v0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: abspattern4:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: abs.4s v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: abspattern4:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v1, #0000000000000000
-; GISEL-NEXT: neg.4s v2, v0
-; GISEL-NEXT: cmge.4s v1, v0, v1
-; GISEL-NEXT: bif.16b v0, v2, v1
-; GISEL-NEXT: ret
-
+; CHECK-GI-LABEL: abspattern4:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
+; CHECK-GI-NEXT: neg.4s v2, v0
+; CHECK-GI-NEXT: cmge.4s v1, v0, v1
+; CHECK-GI-NEXT: bif.16b v0, v2, v1
+; CHECK-GI-NEXT: ret
%tmp1neg = sub <4 x i32> zeroinitializer, %a
%b = icmp sge <4 x i32> %a, zeroinitializer
%abs = select <4 x i1> %b, <4 x i32> %a, <4 x i32> %tmp1neg
@@ -1788,19 +1775,18 @@ define <4 x i32> @abspattern4(<4 x i32> %a) nounwind {
}
define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
-; DAG-LABEL: abspattern5:
-; DAG: // %bb.0:
-; DAG-NEXT: abs.8h v0, v0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: abspattern5:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: abs.8h v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: abspattern5:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v1, #0000000000000000
-; GISEL-NEXT: neg.8h v2, v0
-; GISEL-NEXT: cmgt.8h v1, v0, v1
-; GISEL-NEXT: bif.16b v0, v2, v1
-; GISEL-NEXT: ret
-
+; CHECK-GI-LABEL: abspattern5:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
+; CHECK-GI-NEXT: neg.8h v2, v0
+; CHECK-GI-NEXT: cmgt.8h v1, v0, v1
+; CHECK-GI-NEXT: bif.16b v0, v2, v1
+; CHECK-GI-NEXT: ret
%tmp1neg = sub <8 x i16> zeroinitializer, %a
%b = icmp sgt <8 x i16> %a, zeroinitializer
%abs = select <8 x i1> %b, <8 x i16> %a, <8 x i16> %tmp1neg
@@ -1808,19 +1794,18 @@ define <8 x i16> @abspattern5(<8 x i16> %a) nounwind {
}
define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
-; DAG-LABEL: abspattern6:
-; DAG: // %bb.0:
-; DAG-NEXT: abs.16b v0, v0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: abspattern6:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: abs.16b v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: abspattern6:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v1, #0000000000000000
-; GISEL-NEXT: neg.16b v2, v0
-; GISEL-NEXT: cmgt.16b v1, v1, v0
-; GISEL-NEXT: bit.16b v0, v2, v1
-; GISEL-NEXT: ret
-
+; CHECK-GI-LABEL: abspattern6:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
+; CHECK-GI-NEXT: neg.16b v2, v0
+; CHECK-GI-NEXT: cmgt.16b v1, v1, v0
+; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: ret
%tmp1neg = sub <16 x i8> zeroinitializer, %a
%b = icmp slt <16 x i8> %a, zeroinitializer
%abs = select <16 x i1> %b, <16 x i8> %tmp1neg, <16 x i8> %a
@@ -1828,19 +1813,18 @@ define <16 x i8> @abspattern6(<16 x i8> %a) nounwind {
}
define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
-; DAG-LABEL: abspattern7:
-; DAG: // %bb.0:
-; DAG-NEXT: abs.2d v0, v0
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: abspattern7:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: abs.2d v0, v0
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: abspattern7:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v1, #0000000000000000
-; GISEL-NEXT: neg.2d v2, v0
-; GISEL-NEXT: cmge.2d v1, v1, v0
-; GISEL-NEXT: bit.16b v0, v2, v1
-; GISEL-NEXT: ret
-
+; CHECK-GI-LABEL: abspattern7:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v1, #0000000000000000
+; CHECK-GI-NEXT: neg.2d v2, v0
+; CHECK-GI-NEXT: cmge.2d v1, v1, v0
+; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: ret
%tmp1neg = sub <2 x i64> zeroinitializer, %a
%b = icmp sle <2 x i64> %a, zeroinitializer
%abs = select <2 x i1> %b, <2 x i64> %tmp1neg, <2 x i64> %a
@@ -1848,19 +1832,19 @@ define <2 x i64> @abspattern7(<2 x i64> %a) nounwind {
}
define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
-; DAG-LABEL: uabd_i32:
-; DAG: // %bb.0:
-; DAG-NEXT: sabdl.2d v0, v0, v1
-; DAG-NEXT: ret
+; CHECK-SD-LABEL: uabd_i32:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: sabdl.2d v0, v0, v1
+; CHECK-SD-NEXT: ret
;
-; GISEL-LABEL: uabd_i32:
-; GISEL: // %bb.0:
-; GISEL-NEXT: movi.2d v2, #0000000000000000
-; GISEL-NEXT: ssubl.2d v0, v0, v1
-; GISEL-NEXT: cmgt.2d v1, v2, v0
-; GISEL-NEXT: neg.2d v2, v0
-; GISEL-NEXT: bit.16b v0, v2, v1
-; GISEL-NEXT: ret
+; CHECK-GI-LABEL: uabd_i32:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: movi.2d v2, #0000000000000000
+; CHECK-GI-NEXT: ssubl.2d v0, v0, v1
+; CHECK-GI-NEXT: cmgt.2d v1, v2, v0
+; CHECK-GI-NEXT: neg.2d v2, v0
+; CHECK-GI-NEXT: bit.16b v0, v2, v1
+; CHECK-GI-NEXT: ret
%aext = sext <2 x i32> %a to <2 x i64>
%bext = sext <2 x i32> %b to <2 x i64>
%ab
diff = sub nsw <2 x i64> %aext, %bext
@@ -1870,7 +1854,6 @@ define <2 x i64> @uabd_i32(<2 x i32> %a, <2 x i32> %b) {
ret <2 x i64> %absel
}
-
define <2 x i128> @uabd_i64(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: uabd_i64:
; CHECK: // %bb.0:
@@ -1908,5 +1891,3 @@ define <2 x i128> @uabd_i64(<2 x i64> %a, <2 x i64> %b) {
%absel = select <2 x i1> %abcmp, <2 x i128> %ababs, <2 x i128> %ab
diff
ret <2 x i128> %absel
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; FALLBACK: {{.*}}
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