[PATCH] D154805: [DAGCombiner] Fold IEEE `fmul`/`fdiv` by Pow2 to `add`/`sub` of exp

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Have you looked at using the existing DAG::isKnownToBeAPowerOfTwo and DAGCombiner::BuildLogBase2 methods?



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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:16281
+// 3) The fmul/fdiv add/sub will not go outside of min/max exponent bounds.
+static SDValue combineFMulOrFDivWithIntPow2(DAGCombiner *DC,
+                                            const TargetLowering &TLI,
----------------
Why not make this a DAGCombiner method directly?


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:25191
+      FPVT.getScalarSizeInBits() != IntVT.getScalarSizeInBits())
+    return false;
+
----------------
Add a TODO - as I'm sure we can be more aggressive here, vXi64 uittofp in particular on pre-AVX512 targets, but smaller integers are often worth it since we'd have to extend them any way for the int-to-fp conversion.


Repository:
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  https://reviews.llvm.org/D154805/new/

https://reviews.llvm.org/D154805