[PATCH] D156552: [MachineScheduler] Track physical register dependencies per-regunit

[Jay Foad via Phabricator via llvm-commits]

foad marked 2 inline comments as done.
foad added inline comments.


================
Comment at: llvm/lib/CodeGen/ScheduleDAGInstrs.cpp:225
     for (const MachineBasicBlock *Succ : BB->successors()) {
       for (const auto &LI : Succ->liveins()) {
+        for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
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arsenm wrote:
> liveins should really use regunits too
Not in this patch :)


================
Comment at: llvm/lib/CodeGen/ScheduleDAGInstrs.cpp:226
       for (const auto &LI : Succ->liveins()) {
-        if (!Uses.contains(LI.PhysReg))
-          Uses.insert(PhysRegSUOper(&ExitSU, -1, LI.PhysReg));
+        for (MCRegUnit Unit : TRI->regunits(LI.PhysReg)) {
+          if (!Uses.contains(Unit))
----------------
arsenm wrote:
> This can refine to check the lanemask too
Is there a neat way to iterate regunits for a RegisterMaskPair?


================
Comment at: llvm/lib/CodeGen/ScheduleDAGInstrs.cpp:247
   // "fake" operands added by regalloc.
-  const MCInstrDesc &DefMIDesc = SU->getInstr()->getDesc();
-  bool ImplicitPseudoDef = (OperIdx >= DefMIDesc.getNumOperands() &&
-                            !DefMIDesc.hasImplicitDefOfPhysReg(Reg));
-  for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
-    for (Reg2SUnitsMap::iterator I = Uses.find(*Alias); I != Uses.end(); ++I) {
+  const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
+  bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() &&
----------------
arsenm wrote:
> Don't see why this isn't a reference anymore
That was an oversight.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156552/new/

https://reviews.llvm.org/D156552