[PATCH] D156525: [ThinLTO] Use module hash instead of module ID for cache key

[Nikita Popov via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG279c2971951c: [ThinLTO] Use module hash instead of module ID for cache key (authored by nikic).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156525/new/

https://reviews.llvm.org/D156525

Files:
  llvm/lib/LTO/LTO.cpp
  llvm/test/ThinLTO/X86/Inputs/cache-import-lists3.ll
  llvm/test/ThinLTO/X86/Inputs/cache-import-lists4.ll
  llvm/test/ThinLTO/X86/cache-decoupled-from-order.ll


Index: llvm/test/ThinLTO/X86/cache-decoupled-from-order.ll
===================================================================
--- /dev/null
+++ llvm/test/ThinLTO/X86/cache-decoupled-from-order.ll
@@ -0,0 +1,24 @@
+; RUN: rm -rf %t && mkdir -p %t
+; RUN: opt -module-hash -module-summary %s -o %t/t.bc
+; RUN: opt -module-hash -module-summary %S/Inputs/cache-import-lists3.ll -o %t/a.bc
+; RUN: opt -module-hash -module-summary %S/Inputs/cache-import-lists4.ll -o %t/b.bc
+
+; Tests that the hash for t is insensitive to the order of the modules.
+
+; RUN: llvm-lto2 run -cache-dir %t/cache -o %t.o %t/t.bc %t/a.bc %t/b.bc -r=%t/t.bc,main,plx -r=%t/t.bc,f1,lx -r=%t/t.bc,f2,lx -r=%t/a.bc,f1,plx -r=%t/b.bc,f2,plx
+; RUN: ls %t/cache | count 3
+
+; RUN: llvm-lto2 run -cache-dir %t/cache -o %t.o %t/b.bc %t/a.bc %t/t.bc -r=%t/t.bc,main,plx -r=%t/t.bc,f1,lx -r=%t/t.bc,f2,lx -r=%t/a.bc,f1,plx -r=%t/b.bc,f2,plx
+; RUN: ls %t/cache | count 3
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @main() {
+  call void @f1()
+  call void @f2()
+  ret void
+}
+
+declare void @f1()
+declare void @f2()
Index: llvm/test/ThinLTO/X86/Inputs/cache-import-lists4.ll
===================================================================
--- /dev/null
+++ llvm/test/ThinLTO/X86/Inputs/cache-import-lists4.ll
@@ -0,0 +1,11 @@
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @f2() {
+  call void @internal()
+  ret void
+}
+
+define internal void @internal() {
+  ret void
+}
Index: llvm/test/ThinLTO/X86/Inputs/cache-import-lists3.ll
===================================================================
--- /dev/null
+++ llvm/test/ThinLTO/X86/Inputs/cache-import-lists3.ll
@@ -0,0 +1,11 @@
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+define void @f1() {
+  call void @internal()
+  ret void
+}
+
+define internal void @internal() {
+  ret void
+}
Index: llvm/lib/LTO/LTO.cpp
===================================================================
--- llvm/lib/LTO/LTO.cpp
+++ llvm/lib/LTO/LTO.cpp
@@ -184,7 +184,6 @@
     }
 
     const ModuleHash &getHash() const { return ModInfo->second.second; }
-    uint64_t getId() const { return ModInfo->second.first; }
   };
 
   std::vector<ImportModule> ImportModulesVector;
@@ -194,11 +193,11 @@
        ++It) {
     ImportModulesVector.push_back({It, Index.getModule(It->getKey())});
   }
-  // Order using moduleId integer which is based on the order the module was
-  // added.
+  // Order using module hash, to be both independent of module name and
+  // module order.
   llvm::sort(ImportModulesVector,
              [](const ImportModule &Lhs, const ImportModule &Rhs) -> bool {
-               return Lhs.getId() < Rhs.getId();
+               return Lhs.getHash() < Rhs.getHash();
              });
   for (const ImportModule &Entry : ImportModulesVector) {
     auto ModHash = Entry.getHash();


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