[PATCH] D156538: [AArch64] Try to combine FMUL with FDIV

[JinGu Kang via Phabricator via llvm-commits]

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gcc generates less instructions than llvm from below example.

  float foo(int state) {
      return (float)state / 2;
  }

gcc output

  foo:
    scvtf s0, w0, #1
    ret

llvm output

  foo:
    scvtf s0, w0
    fmov s1, #0.50000000
    fmul s0, s0, s1
    ret

gcc converts the float division to float multiplication like `X / C --> X * (1 / C)`, and it has a pattern with float multiplication for `scvtf` as below.

  ;; Equal width integer to fp and multiply combine.
  (define_insn "*aarch64_<su_optab>cvtf<fcvt_target><GPF:mode>2_mult"
    [(set (match_operand:GPF 0 "register_operand" "=w,w")
          (mult:GPF (FLOATUORS:GPF
                     (match_operand:<FCVT_TARGET> 1 "register_operand" "w,?r"))
                     (match_operand:GPF 2 "aarch64_fp_pow2_recip" "Dt,Dt")))]
    "TARGET_FLOAT"
    {
      operands[2] = GEN_INT (aarch64_fpconst_pow2_recip (operands[2]));
      switch (which_alternative)
      {    
        case 0:
          return "<su_optab>cvtf\t%<GPF:s>0, %<s>1, #%2";
        case 1:
          return "<su_optab>cvtf\t%<GPF:s>0, %<w1>1, #%2";
        default:
          gcc_unreachable ();
      }    
    }
    [(set_attr "type" "neon_int_to_fp_<Vetype>,f_cvti2f")
     (set_attr "arch" "simd,fp")]
  )

llvm also converts fdiv to fmul in InstCombine pass like `X / C --> X * (1 / C)` but it does not have ISel codes with `fmul` for `scvtf`.
If fmul's constant operand is the reciprocal of a power of 2 like `(1/2^n)` and the other operand is SINT_TO_FP, we can try `X * (1 / C) --> X / C` because it will be matched with `scvtf` patterns with fixed-point.
With this patch, the llvm's output is as below.

  foo:
          scvtf   s0, w0, #1
          ret


https://reviews.llvm.org/D156538

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/svtcf-fmul-fdiv-combine.ll

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