[llvm] d5f496a - Revert "[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF"
Kevin Athey via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 28 03:25:18 PDT 2023
Author: Kevin Athey
Date: 2023-07-28T12:23:18+02:00
New Revision: d5f496a2cb4dd3b032c5f53c86222a54eb0f0806
URL: https://github.com/llvm/llvm-project/commit/d5f496a2cb4dd3b032c5f53c86222a54eb0f0806
DIFF: https://github.com/llvm/llvm-project/commit/d5f496a2cb4dd3b032c5f53c86222a54eb0f0806.diff
LOG: Revert "[RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF"
This reverts commit 9cf675923afa73a3dbe575803ebbbe9146701df8.
Breaking sanitzer buildbots: asan and fast
https://lab.llvm.org/buildbot/#/builders/168/builds/14824
https://lab.llvm.org/buildbot/#/builders/5/builds/35419
Added:
Modified:
llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
Removed:
llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
index 3bb1161f9b7042..fed3fa2987e52f 100644
--- a/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
@@ -118,57 +118,65 @@ static unsigned getUndefInitOpcode(unsigned RegClassID) {
}
}
-static bool isEarlyClobberMI(MachineInstr &MI) {
- return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
- return DefMO.isReg() && DefMO.isEarlyClobber();
- });
-}
-
bool RISCVInitUndef::handleImplicitDef(MachineBasicBlock &MBB,
MachineBasicBlock::iterator &Inst) {
+ const TargetRegisterInfo &TRI =
+ *MBB.getParent()->getSubtarget().getRegisterInfo();
+
assert(Inst->getOpcode() == TargetOpcode::IMPLICIT_DEF);
Register Reg = Inst->getOperand(0).getReg();
if (!Reg.isVirtual())
return false;
- bool HasOtherUse = false;
+ bool NeedPseudoInit = false;
SmallVector<MachineOperand *, 1> UseMOs;
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
- if (isEarlyClobberMI(*MO.getParent())) {
- if (MO.isUse() && !MO.isTied())
- UseMOs.push_back(&MO);
- else
- HasOtherUse = true;
+ MachineInstr *UserMI = MO.getParent();
+
+ bool HasEarlyClobber = false;
+ bool TiedToDef = false;
+ for (MachineOperand &UserMO : UserMI->operands()) {
+ if (!UserMO.isReg())
+ continue;
+ if (UserMO.isEarlyClobber())
+ HasEarlyClobber = true;
+ if (UserMO.isUse() && UserMO.isTied() &&
+ TRI.regsOverlap(UserMO.getReg(), Reg))
+ TiedToDef = true;
+ }
+ if (HasEarlyClobber && !TiedToDef) {
+ NeedPseudoInit = true;
+ UseMOs.push_back(&MO);
}
}
- if (UseMOs.empty())
+ if (!NeedPseudoInit)
return false;
LLVM_DEBUG(
dbgs() << "Emitting PseudoRVVInitUndef for implicit vector register "
<< Reg << '\n');
- const TargetRegisterClass *TargetRegClass =
- getVRLargestSuperClass(MRI->getRegClass(Reg));
- unsigned Opcode = getUndefInitOpcode(TargetRegClass->getID());
+ unsigned RegClassID = getVRLargestSuperClass(MRI->getRegClass(Reg))->getID();
+ unsigned Opcode = getUndefInitOpcode(RegClassID);
- Register NewDest = Reg;
- if (HasOtherUse)
- NewDest = MRI->createVirtualRegister(TargetRegClass);
- BuildMI(MBB, Inst, Inst->getDebugLoc(), TII->get(Opcode), NewDest);
+ BuildMI(MBB, Inst, Inst->getDebugLoc(), TII->get(Opcode), Reg);
- if (!HasOtherUse)
- Inst = MBB.erase(Inst);
+ Inst = MBB.erase(Inst);
- for (auto MO : UseMOs) {
- MO->setReg(NewDest);
+ for (auto MO : UseMOs)
MO->setIsUndef(false);
- }
+
return true;
}
+static bool isEarlyClobberMI(MachineInstr &MI) {
+ return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) {
+ return DefMO.isReg() && DefMO.isEarlyClobber();
+ });
+}
+
bool RISCVInitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
const DeadLaneDetector &DLD) {
bool Changed = false;
diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
index 1fe6ecd6fcbc68..336136c0aa28c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
@@ -1,17 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv64 -mattr=+v -riscv-enable-subreg-liveness < %s | FileCheck %s
-define <vscale x 2 x float> @vrgather_all_undef(ptr %p) {
-; CHECK-LABEL: vrgather_all_undef:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsetivli zero, 0, e32, m1, ta, ma
-; CHECK-NEXT: vrgather.vi v8, v9, 0
-; CHECK-NEXT: ret
-entry:
- %0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> undef, i64 0, i64 0)
- ret <vscale x 2 x float> %0
-}
-
define dso_local signext i32 @undef_early_clobber_chain() {
; CHECK-LABEL: undef_early_clobber_chain:
; CHECK: # %bb.0: # %entry
@@ -36,14 +25,14 @@ entry:
define internal void @SubRegLivenessUndefInPhi(i64 %cond) {
; CHECK-LABEL: SubRegLivenessUndefInPhi:
; CHECK: # %bb.0: # %start
-; CHECK-NEXT: blez a0, .LBB2_2
+; CHECK-NEXT: blez a0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %Cond1
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vi v10, v8, 1
; CHECK-NEXT: vadd.vi v12, v8, 3
-; CHECK-NEXT: j .LBB2_3
-; CHECK-NEXT: .LBB2_2: # %Cond2
+; CHECK-NEXT: j .LBB1_3
+; CHECK-NEXT: .LBB1_2: # %Cond2
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v9
; CHECK-NEXT: csrr a0, vlenb
@@ -59,7 +48,7 @@ define internal void @SubRegLivenessUndefInPhi(i64 %cond) {
; CHECK-NEXT: vadd.vi v9, v9, 3
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vx v12, v9, a0
-; CHECK-NEXT: .LBB2_3: # %UseSR
+; CHECK-NEXT: .LBB1_3: # %UseSR
; CHECK-NEXT: vl1r.v v14, (zero)
; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma
; CHECK-NEXT: vrgatherei16.vv v13, v14, v8
@@ -115,7 +104,7 @@ define internal void @SubRegLivenessUndef() {
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vi v10, v8, 1
; CHECK-NEXT: vadd.vi v12, v8, 3
-; CHECK-NEXT: .LBB3_1: # %loopIR3.i.i
+; CHECK-NEXT: .LBB2_1: # %loopIR3.i.i
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vl1r.v v14, (zero)
; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma
@@ -128,7 +117,7 @@ define internal void @SubRegLivenessUndef() {
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT: vand.vv v9, v9, v11
; CHECK-NEXT: vs1r.v v9, (zero)
-; CHECK-NEXT: j .LBB3_1
+; CHECK-NEXT: j .LBB2_1
loopIR.preheader.i.i:
%v15 = tail call <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
%v17 = tail call <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16> poison, <vscale x 1 x i16> %v15, i64 0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
deleted file mode 100644
index 08ea967179ebf8..00000000000000
--- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir
+++ /dev/null
@@ -1,91 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple=riscv32 -mattr=+v -riscv-enable-subreg-liveness -run-pass riscv-init-undef -run-pass machineverifier %s -o - | FileCheck %s
-
---- |
- source_filename = "<stdin>"
- target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128"
- target triple = "riscv64"
-
- define <vscale x 2 x float> @undef_early_clobber_chain(ptr %p) #0 {
- entry:
- %0 = tail call <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float> undef, <vscale x 2 x float> undef, i64 0, i64 0)
- ret <vscale x 2 x float> %0
- }
-
- declare <vscale x 2 x float> @llvm.riscv.vrgather.vx.nxv2f32.i64(<vscale x 2 x float>, <vscale x 2 x float>, i64, i64) #1
-
- attributes #0 = { "target-features"="+v" }
- attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) "target-features"="+v" }
-
-...
----
-name: undef_early_clobber_chain
-alignment: 4
-exposesReturnsTwice: false
-legalized: false
-regBankSelected: false
-selected: false
-failedISel: false
-tracksRegLiveness: true
-hasWinCFI: false
-callsEHReturn: false
-callsUnwindInit: false
-hasEHCatchret: false
-hasEHScopes: false
-hasEHFunclets: false
-isOutlined: false
-debugInstrRef: false
-failsVerification: false
-tracksDebugUserValues: false
-registers:
- - { id: 0, class: gpr, preferred-register: '' }
- - { id: 1, class: vr, preferred-register: '' }
- - { id: 2, class: vr, preferred-register: '' }
- - { id: 3, class: vr, preferred-register: '' }
-liveins: []
-frameInfo:
- isFrameAddressTaken: false
- isReturnAddressTaken: false
- hasStackMap: false
- hasPatchPoint: false
- stackSize: 0
- offsetAdjustment: 0
- maxAlignment: 1
- adjustsStack: false
- hasCalls: false
- stackProtector: ''
- functionContext: ''
- maxCallFrameSize: 4294967295
- cvBytesOfCalleeSavedRegisters: 0
- hasOpaqueSPAdjustment: false
- hasVAStart: false
- hasMustTailInVarArgFunc: false
- hasTailCall: false
- localFrameSize: 0
- savePoint: ''
- restorePoint: ''
-fixedStack: []
-stack: []
-entry_values: []
-callSites: []
-debugValueSubstitutions: []
-constants: []
-machineFunctionInfo:
- varArgsFrameIndex: 0
- varArgsSaveSize: 0
-body: |
- bb.0.entry:
- ; CHECK-LABEL: name: undef_early_clobber_chain
- ; CHECK: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
- ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- ; CHECK-NEXT: early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef [[DEF]], [[PseudoRVVInitUndefM1_]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
- ; CHECK-NEXT: $v8 = COPY %1
- ; CHECK-NEXT: PseudoRET implicit $v8
- %2:vr = IMPLICIT_DEF
- dead $x0 = PseudoVSETIVLI 0, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
- early-clobber %1:vr = PseudoVRGATHER_VI_M1 undef %2, undef %2, 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
- $v8 = COPY %1
- PseudoRET implicit $v8
-
-...
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