[llvm] 092e60a - [RISCV] Add support for XCValu extension in CV32E40P
QIHAN CAI via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 27 20:37:40 PDT 2023
Author: Qihan Cai
Date: 2023-07-28T11:37:31+08:00
New Revision: 092e60a3fcb642e0a1d08c4c30722995573c7d4d
URL: https://github.com/llvm/llvm-project/commit/092e60a3fcb642e0a1d08c4c30722995573c7d4d
DIFF: https://github.com/llvm/llvm-project/commit/092e60a3fcb642e0a1d08c4c30722995573c7d4d.diff
LOG: [RISCV] Add support for XCValu extension in CV32E40P
Implement XCValu intrinsics for CV32E40P according to the specification.
This is a commit of the patch-set to upstream the 7 vendor specific extensions of CV32E40P.
Contributors: @CharKeaney, Nandni Jamnadas, Serkan Muhcu, @jeremybennett, @lewis-revill, @liaolucy, @simoncook, @xmj
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D153748
Added:
llvm/test/MC/RISCV/corev/XCValu-invalid.s
llvm/test/MC/RISCV/corev/XCValu-valid.s
Modified:
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
Removed:
################################################################################
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 86da02b4d5fd13..b9f9138f2404c9 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -271,5 +271,8 @@ The current vendor extensions supported are:
``XCVmac``
LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group. All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
+``XCValu``
+ LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
+
``XSfcie``
LLVM implements `version 1.0.0 of the SiFive Custom Instruction Extension (CIE) Software Specification <https://sifive.cdn.prismic.io/sifive/767804da-53b2-4893-97d5-b7c030ae0a94_s76mc_core_complex_manual_21G3.pdf>`_ by SiFive. All custom instruction are added as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for S76 processor at this time.
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
index f3d35ae4cd6aba..f0bae51ec1edf9 100644
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -66,6 +66,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
{"v", RISCVExtensionVersion{1, 0}},
// vendor-defined ('X') extensions
+ {"xcvalu", RISCVExtensionVersion{1, 0}},
{"xcvbitmanip", RISCVExtensionVersion{1, 0}},
{"xcvmac", RISCVExtensionVersion{1, 0}},
{"xsfcie", RISCVExtensionVersion{1, 0}},
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index e6ea6baa72ff47..057706804d7b50 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -565,6 +565,8 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
"CORE-V Bit Manipulation custom opcode table");
TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32,
"CORE-V MAC custom opcode table");
+ TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32,
+ "CORE-V ALU custom opcode table");
TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table");
return MCDisassembler::Fail;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index f10f97dc5ca6e8..51c2986ea87a21 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -802,6 +802,13 @@ def HasVendorXCVmac : Predicate<"Subtarget->hasVendorXCVmac()">,
AssemblerPredicate<(all_of FeatureVendorXCVmac),
"'XCVmac' (CORE-V Multiply-Accumulate)">;
+def FeatureVendorXCValu
+ : SubtargetFeature<"xcvalu", "HasVendorXCValu", "true",
+ "'XCValu' (CORE-V ALU Operations)">;
+def HasVendorXCValu : Predicate<"Subtarget->hasVendorXCValu()">,
+ AssemblerPredicate<(all_of FeatureVendorXCValu),
+ "'XCValu' (CORE-V ALU Operations)">;
+
//===----------------------------------------------------------------------===//
// LLVM specific features and extensions
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
index 32b1ba9a09844a..a92eb1e8ba82e8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
@@ -60,7 +60,7 @@ let Predicates = [HasVendorXCVbitmanip, IsRV32],
def CV_BCLRR : CVBitManipRR<0b0011100, "cv.bclrr">;
def CV_BSETR : CVBitManipRR<0b0011101, "cv.bsetr">;
- def CV_ROR : CVBitManipRR<0b0100000, "cv.ror">;
+ def CVROR : CVBitManipRR<0b0100000, "cv.ror">;
def CV_FF1 : CVBitManipR<0b0100001, "cv.ff1">;
def CV_FL1 : CVBitManipR<0b0100010, "cv.fl1">;
def CV_CLB : CVBitManipR<0b0100011, "cv.clb">;
@@ -166,3 +166,130 @@ let Predicates = [HasVendorXCVmac, IsRV32] in {
def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
(CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
} // Predicates = [HasVendorXCVmac, IsRV32]
+
+let DecoderNamespace = "XCValu" in {
+ class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
+ : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
+ opcodestr, "$rd, $rs1, $rs2, $imm5", [], InstFormatOther> {
+ bits<5> imm5;
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-30} = funct2;
+ let Inst{29-25} = imm5;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = OPC_CUSTOM_2.Value;
+ }
+
+ class CVInstAluRR<bits<7> funct7, bits<3> funct3, string opcodestr>
+ : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
+ (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+ class CVInstAluRRNR<bits<7> funct7, bits<3> funct3, string opcodestr>
+ : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd_wb),
+ (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
+
+ class CVInstAluRI<bits<7> funct7, bits<3> funct3, string opcodestr>
+ : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5), opcodestr,
+ "$rd, $rs1, $imm5", [], InstFormatOther> {
+ bits<5> imm5;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31-25} = funct7;
+ let Inst{24-20} = imm5;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = funct3;
+ let Inst{11-7} = rd;
+ let Inst{6-0} = OPC_CUSTOM_1.Value;
+ }
+
+ class CVInstAluR<bits<7> funct7, bits<3> funct3, string opcodestr>
+ : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins GPR:$rs1),
+ opcodestr, "$rd, $rs1"> {
+ let rs2 = 0b00000;
+ }
+
+} // DecoderNamespace = "XCValu"
+
+let Predicates = [HasVendorXCValu],
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+ // General ALU Operations
+ def CV_ABS : CVInstAluR<0b0101000, 0b011, "cv.abs">,
+ Sched<[]>;
+ def CV_SLET : CVInstAluRR<0b0101001, 0b011, "cv.slet">,
+ Sched<[]>;
+ def CV_SLETU : CVInstAluRR<0b0101010, 0b011, "cv.sletu">,
+ Sched<[]>;
+ def CV_MIN : CVInstAluRR<0b0101011, 0b011, "cv.min">,
+ Sched<[]>;
+ def CV_MINU : CVInstAluRR<0b0101100, 0b011, "cv.minu">,
+ Sched<[]>;
+ def CV_MAX : CVInstAluRR<0b0101101, 0b011, "cv.max">,
+ Sched<[]>;
+ def CV_MAXU : CVInstAluRR<0b0101110, 0b011, "cv.maxu">,
+ Sched<[]>;
+ def CV_EXTHS : CVInstAluR<0b0110000, 0b011, "cv.exths">,
+ Sched<[]>;
+ def CV_EXTHZ : CVInstAluR<0b0110001, 0b011, "cv.exthz">,
+ Sched<[]>;
+ def CV_EXTBS : CVInstAluR<0b0110010, 0b011, "cv.extbs">,
+ Sched<[]>;
+ def CV_EXTBZ : CVInstAluR<0b0110011, 0b011, "cv.extbz">,
+ Sched<[]>;
+
+ def CV_CLIP : CVInstAluRI<0b0111000, 0b011, "cv.clip">,
+ Sched<[]>;
+ def CV_CLIPU : CVInstAluRI<0b0111001, 0b011, "cv.clipu">,
+ Sched<[]>;
+ def CV_CLIPR : CVInstAluRR<0b0111010, 0b011, "cv.clipr">,
+ Sched<[]>;
+ def CV_CLIPUR : CVInstAluRR<0b0111011, 0b011, "cv.clipur">,
+ Sched<[]>;
+
+ def CV_ADDN : CVInstAluRRI<0b00, 0b010, "cv.addn">,
+ Sched<[]>;
+ def CV_ADDUN : CVInstAluRRI<0b01, 0b010, "cv.addun">,
+ Sched<[]>;
+ def CV_ADDRN : CVInstAluRRI<0b10, 0b010, "cv.addrn">,
+ Sched<[]>;
+ def CV_ADDURN : CVInstAluRRI<0b11, 0b010, "cv.addurn">,
+ Sched<[]>;
+ def CV_SUBN : CVInstAluRRI<0b00, 0b011, "cv.subn">,
+ Sched<[]>;
+ def CV_SUBUN : CVInstAluRRI<0b01, 0b011, "cv.subun">,
+ Sched<[]>;
+ def CV_SUBRN : CVInstAluRRI<0b10, 0b011, "cv.subrn">,
+ Sched<[]>;
+ def CV_SUBURN : CVInstAluRRI<0b11, 0b011, "cv.suburn">,
+ Sched<[]>;
+} // Predicates = [HasVendorXCValu],
+ // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let Predicates = [HasVendorXCValu],
+ hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+ Constraints = "$rd = $rd_wb" in {
+ def CV_ADDNR : CVInstAluRRNR<0b1000000, 0b011, "cv.addnr">,
+ Sched<[]>;
+ def CV_ADDUNR : CVInstAluRRNR<0b1000001, 0b011, "cv.addunr">,
+ Sched<[]>;
+ def CV_ADDRNR : CVInstAluRRNR<0b1000010, 0b011, "cv.addrnr">,
+ Sched<[]>;
+ def CV_ADDURNR : CVInstAluRRNR<0b1000011, 0b011, "cv.addurnr">,
+ Sched<[]>;
+ def CV_SUBNR : CVInstAluRRNR<0b1000100, 0b011, "cv.subnr">,
+ Sched<[]>;
+ def CV_SUBUNR : CVInstAluRRNR<0b1000101, 0b011, "cv.subunr">,
+ Sched<[]>;
+ def CV_SUBRNR : CVInstAluRRNR<0b1000110, 0b011, "cv.subrnr">,
+ Sched<[]>;
+ def CV_SUBURNR : CVInstAluRRNR<0b1000111, 0b011, "cv.suburnr">,
+ Sched<[]>;
+
+} // Predicates = [HasVendorXCValu],
+ // hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+ // Constraints = "$rd = $rd_wb"
diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll
index 183c942cf0a010..b0d5925ec36aa6 100644
--- a/llvm/test/CodeGen/RISCV/attributes.ll
+++ b/llvm/test/CodeGen/RISCV/attributes.ll
@@ -41,6 +41,7 @@
; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s
; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s
; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s
+; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvbitmanip %s -o - | FileCheck --check-prefix=RV32XCVBITMANIP %s
; RUN: llc -mtriple=riscv32 -mattr=+xcvmac %s -o - | FileCheck --check-prefix=RV32XCVMAC %s
; RUN: llc -mtriple=riscv32 -mattr=+xtheadcmo %s -o - | FileCheck --check-prefix=RV32XTHEADCMO %s
@@ -214,6 +215,7 @@
; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0"
; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0"
; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0"
+; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0"
; RV32XCVBITMANIP: .attribute 5, "rv32i2p1_xcvbitmanip1p0"
; RV32XCVMAC: .attribute 5, "rv32i2p1_xcvmac1p0"
; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0"
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
index b6983faee200a8..91df42449c4cca 100644
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -285,6 +285,9 @@
.attribute arch, "rv32izacas1p0"
# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
+.attribute arch, "rv32i_xcvalu"
+# CHECK: attribute 5, "rv32i2p1_xcvalu1p0"
+
.attribute arch, "rv32i_xcvbitmanip"
# CHECK: attribute 5, "rv32i2p1_xcvbitmanip1p0"
diff --git a/llvm/test/MC/RISCV/corev/XCValu-invalid.s b/llvm/test/MC/RISCV/corev/XCValu-invalid.s
new file mode 100644
index 00000000000000..550d79c44f6b85
--- /dev/null
+++ b/llvm/test/MC/RISCV/corev/XCValu-invalid.s
@@ -0,0 +1,536 @@
+# RUN: not llvm-mc -triple=riscv32 --mattr=+xcvalu %s 2>&1 \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ERROR
+
+cv.addrnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addrnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbz t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbz 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbz t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extbz t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipu t0, t1, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clipu t0, t1, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clipu t0, t1, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clipu t0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipu 0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clipu t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.minu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.minu t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.abs t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.abs t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.suburn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.suburn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.suburn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.suburn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clip t0, t1, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clip t0, t1, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clip t0, t1, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.clip t0, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clip 0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clip t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clip t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addunr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addunr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addurn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addurn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addurn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addurn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subun t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subun t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subun t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subun t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.subun t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.subn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.subrnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.slet t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.slet t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.suburnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.suburnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.maxu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.maxu t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbs t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbs 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.extbs t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.extbs t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exths t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exths 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exths t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.exths t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.max t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.max t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subunr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.subunr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exthz t0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exthz 0, t1
+# CHECK-ERROR: invalid operand for instruction
+
+cv.exthz t0
+# CHECK-ERROR: too few operands for instruction
+
+cv.exthz t0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipur t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clipur t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addurnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.addurnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.addn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.addn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.addn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn t0, t1, t2, -1
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subrn t0, t1, t2, 32
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subrn t0, t1, t2, a0
+# CHECK-ERROR: immediate must be an integer in the range [0, 31]
+
+cv.subrn t0, t1, 0, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn t0, 0, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn 0, t1, t2, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subrn t0, t1, t2
+# CHECK-ERROR: too few operands for instruction
+
+cv.subrn t0, t1, t2, 0, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.subnr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.subnr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.clipr t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.clipr t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.sletu t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.sletu t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min t0, t1, 0
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min t0, 0, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min 0, t1, t2
+# CHECK-ERROR: invalid operand for instruction
+
+cv.min t0, t1
+# CHECK-ERROR: too few operands for instruction
+
+cv.min t0, t1, t2, a0
+# CHECK-ERROR: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/corev/XCValu-valid.s b/llvm/test/MC/RISCV/corev/XCValu-valid.s
new file mode 100644
index 00000000000000..15fe0adf14ac0e
--- /dev/null
+++ b/llvm/test/MC/RISCV/corev/XCValu-valid.s
@@ -0,0 +1,367 @@
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvalu -riscv-no-aliases -show-encoding %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvalu < %s \
+# RUN: | llvm-objdump --mattr=+xcvalu -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-INSTR %s
+# RUN: not llvm-mc -triple riscv32 %s 2>&1 \
+# RUN: | FileCheck -check-prefix=CHECK-NO-EXT %s
+
+cv.addurnr t0, t1, t2
+# CHECK-INSTR: cv.addurnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x86]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurnr a0, a1, a2
+# CHECK-INSTR: cv.addurnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x86]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.maxu t0, t1, t2
+# CHECK-INSTR: cv.maxu t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x5c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.maxu a0, a1, a2
+# CHECK-INSTR: cv.maxu a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x5c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrnr t0, t1, t2
+# CHECK-INSTR: cv.subrnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x8c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrnr a0, a1, a2
+# CHECK-INSTR: cv.subrnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8c]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.slet t0, t1, t2
+# CHECK-INSTR: cv.slet t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x52]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.slet a0, a1, a2
+# CHECK-INSTR: cv.slet a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x52]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrn t0, t1, t2, 0
+# CHECK-INSTR: cv.subrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrn t0, t1, t2, 16
+# CHECK-INSTR: cv.subrn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subrn a0, a1, zero, 31
+# CHECK-INSTR: cv.subrn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subnr t0, t1, t2
+# CHECK-INSTR: cv.subnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x88]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subnr a0, a1, a2
+# CHECK-INSTR: cv.subnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x88]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addunr t0, t1, t2
+# CHECK-INSTR: cv.addunr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x82]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addunr a0, a1, a2
+# CHECK-INSTR: cv.addunr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x82]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurn t0, t1, t2, 0
+# CHECK-INSTR: cv.addurn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurn t0, t1, t2, 16
+# CHECK-INSTR: cv.addurn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addurn a0, a1, zero, 31
+# CHECK-INSTR: cv.addurn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addun t0, t1, t2, 0
+# CHECK-INSTR: cv.addun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addun t0, t1, t2, 16
+# CHECK-INSTR: cv.addun t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addun a0, a1, zero, 31
+# CHECK-INSTR: cv.addun a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipu t0, t1, 0
+# CHECK-INSTR: cv.clipu t0, t1, 0
+# CHECK-ENCODING: [0xab,0x32,0x03,0x72]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipu t0, t1, 16
+# CHECK-INSTR: cv.clipu t0, t1, 16
+# CHECK-ENCODING: [0xab,0x32,0x03,0x73]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipu a0, zero, 31
+# CHECK-INSTR: cv.clipu a0, zero, 31
+# CHECK-ENCODING: [0x2b,0x35,0xf0,0x73]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clip t0, t1, 0
+# CHECK-INSTR: cv.clip t0, t1, 0
+# CHECK-ENCODING: [0xab,0x32,0x03,0x70]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clip t0, t1, 16
+# CHECK-INSTR: cv.clip t0, t1, 16
+# CHECK-ENCODING: [0xab,0x32,0x03,0x71]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clip a0, zero, 31
+# CHECK-INSTR: cv.clip a0, zero, 31
+# CHECK-ENCODING: [0x2b,0x35,0xf0,0x71]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exthz t0, t1
+# CHECK-INSTR: cv.exthz t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x62]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exthz a0, a1
+# CHECK-INSTR: cv.exthz a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x62]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.max t0, t1, t2
+# CHECK-INSTR: cv.max t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x5a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.max a0, a1, a2
+# CHECK-INSTR: cv.max a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x5a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipr t0, t1, t2
+# CHECK-INSTR: cv.clipr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x74]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipr a0, a1, a2
+# CHECK-INSTR: cv.clipr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x74]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subn t0, t1, t2, 0
+# CHECK-INSTR: cv.subn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subn t0, t1, t2, 16
+# CHECK-INSTR: cv.subn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subn a0, a1, zero, 31
+# CHECK-INSTR: cv.subn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbz t0, t1
+# CHECK-INSTR: cv.extbz t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x66]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbz a0, a1
+# CHECK-INSTR: cv.extbz a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x66]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.abs t0, t1
+# CHECK-INSTR: cv.abs t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x50]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.abs a0, a1
+# CHECK-INSTR: cv.abs a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x50]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipur t0, t1, t2
+# CHECK-INSTR: cv.clipur t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x76]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.clipur a0, a1, a2
+# CHECK-INSTR: cv.clipur a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x76]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.minu t0, t1, t2
+# CHECK-INSTR: cv.minu t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x58]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.minu a0, a1, a2
+# CHECK-INSTR: cv.minu a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x58]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addn t0, t1, t2, 0
+# CHECK-INSTR: cv.addn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x00]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addn t0, t1, t2, 16
+# CHECK-INSTR: cv.addn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x20]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addn a0, a1, zero, 31
+# CHECK-INSTR: cv.addn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0x3e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subunr t0, t1, t2
+# CHECK-INSTR: cv.subunr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x8a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subunr a0, a1, a2
+# CHECK-INSTR: cv.subunr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8a]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbs t0, t1
+# CHECK-INSTR: cv.extbs t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x64]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.extbs a0, a1
+# CHECK-INSTR: cv.extbs a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x64]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.sletu t0, t1, t2
+# CHECK-INSTR: cv.sletu t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x54]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.sletu a0, a1, a2
+# CHECK-INSTR: cv.sletu a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x54]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.min t0, t1, t2
+# CHECK-INSTR: cv.min t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x56]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.min a0, a1, a2
+# CHECK-INSTR: cv.min a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x56]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburnr t0, t1, t2
+# CHECK-INSTR: cv.suburnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x8e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburnr a0, a1, a2
+# CHECK-INSTR: cv.suburnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x8e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrnr t0, t1, t2
+# CHECK-INSTR: cv.addrnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x84]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrnr a0, a1, a2
+# CHECK-INSTR: cv.addrnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x84]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exths t0, t1
+# CHECK-INSTR: cv.exths t0, t1
+# CHECK-ENCODING: [0xab,0x32,0x03,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.exths a0, a1
+# CHECK-INSTR: cv.exths a0, a1
+# CHECK-ENCODING: [0x2b,0xb5,0x05,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrn t0, t1, t2, 0
+# CHECK-INSTR: cv.addrn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x22,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrn t0, t1, t2, 16
+# CHECK-INSTR: cv.addrn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x22,0x73,0xa0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addrn a0, a1, zero, 31
+# CHECK-INSTR: cv.addrn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xa5,0x05,0xbe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburn t0, t1, t2, 0
+# CHECK-INSTR: cv.suburn t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0xc0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburn t0, t1, t2, 16
+# CHECK-INSTR: cv.suburn t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0xe0]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.suburn a0, a1, zero, 31
+# CHECK-INSTR: cv.suburn a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0xfe]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addnr t0, t1, t2
+# CHECK-INSTR: cv.addnr t0, t1, t2
+# CHECK-ENCODING: [0xab,0x32,0x73,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.addnr a0, a1, a2
+# CHECK-INSTR: cv.addnr a0, a1, a2
+# CHECK-ENCODING: [0x2b,0xb5,0xc5,0x80]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subun t0, t1, t2, 0
+# CHECK-INSTR: cv.subun t0, t1, t2, 0
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x40]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subun t0, t1, t2, 16
+# CHECK-INSTR: cv.subun t0, t1, t2, 16
+# CHECK-ENCODING: [0xdb,0x32,0x73,0x60]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
+
+cv.subun a0, a1, zero, 31
+# CHECK-INSTR: cv.subun a0, a1, zero, 31
+# CHECK-ENCODING: [0x5b,0xb5,0x05,0x7e]
+# CHECK-NO-EXT: instruction requires the following: 'XCValu' (CORE-V ALU Operations){{$}}
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