[PATCH] D156491: [RA] Split a virtual register in cold blocks if it is not assigned preferred physical register

[Guozhi Wei via Phabricator via llvm-commits]

Carrot created this revision.
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If a virtual register is not assigned preferred physical register, it means some COPY instructions will be changed to real register move instructions. In this case we can try to split the virtual register in colder blocks, if success, the original COPY instructions can be deleted, and the new COPY instructions in colder blocks will be generated as register move instructions. It results in fewer dynamic register move instructions executed.

The new test case split-reg-with-hint.ll gives an example, the hot path contains 24 instructions without this patch, now it is only 4 instructions with this patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156491

Files:
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/lib/CodeGen/RegAllocGreedy.h
  llvm/test/CodeGen/AArch64/cgp-usubo.ll
  llvm/test/CodeGen/AArch64/csr-split.ll
  llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
  llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir
  llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
  llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
  llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
  llvm/test/CodeGen/ARM/csr-split.ll
  llvm/test/CodeGen/ARM/divmod-eabi.ll
  llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
  llvm/test/CodeGen/ARM/thumb2-size-opt.ll
  llvm/test/CodeGen/AVR/cttz.ll
  llvm/test/CodeGen/Hexagon/noreturn-noepilog.ll
  llvm/test/CodeGen/LoongArch/exception-pointer-register.ll
  llvm/test/CodeGen/PowerPC/csr-split.ll
  llvm/test/CodeGen/PowerPC/ppc64-rop-protection-aix.ll
  llvm/test/CodeGen/PowerPC/ppc64-rop-protection.ll
  llvm/test/CodeGen/PowerPC/subreg-postra.ll
  llvm/test/CodeGen/PowerPC/tail-dup-break-cfg.ll
  llvm/test/CodeGen/PowerPC/tls-cse.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/exception-pointer-register.ll
  llvm/test/CodeGen/RISCV/float-round-conv-sat.ll
  llvm/test/CodeGen/RISCV/fmax-fmin.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll
  llvm/test/CodeGen/RISCV/overflow-intrinsics.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-vpload.ll
  llvm/test/CodeGen/Thumb2/constant-islands-cbz.ll
  llvm/test/CodeGen/Thumb2/pacbti-m-outliner-3.ll
  llvm/test/CodeGen/X86/2007-11-30-LoadFolding-Bug.ll
  llvm/test/CodeGen/X86/avoid-sfb.ll
  llvm/test/CodeGen/X86/cgp-usubo.ll
  llvm/test/CodeGen/X86/csr-split.ll
  llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
  llvm/test/CodeGen/X86/peep-test-4.ll
  llvm/test/CodeGen/X86/ragreedy-bug.ll
  llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll
  llvm/test/CodeGen/X86/speculative-load-hardening.ll
  llvm/test/CodeGen/X86/split-reg-with-hint.ll
  llvm/test/CodeGen/X86/statepoint-call-lowering.ll
  llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir
  llvm/test/CodeGen/X86/statepoint-ra.ll
  llvm/test/CodeGen/X86/statepoint-vreg-details.ll
  llvm/test/CodeGen/X86/statepoint-vreg.ll
  llvm/test/CodeGen/X86/xmulo.ll
  llvm/test/DebugInfo/ARM/sdag-split-arg.ll
  llvm/test/DebugInfo/X86/live-debug-values.ll
  llvm/test/tools/llvm-objdump/XCOFF/disassemble-symbolize-operands.ll

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