[PATCH] D155772: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types

[Nitin John Raj via Phabricator via llvm-commits]

nitinjohnraj marked 5 inline comments as done.
nitinjohnraj added inline comments.


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Comment at: llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp:34
+      .legalFor({XLenLLT, XLenLLT})
+      .clampScalar(1, XLenLLT, XLenLLT)
+      .clampScalar(0, XLenLLT, XLenLLT);
----------------
tschuett wrote:
> You claim: " types narrower and upto XLen". But you clamp to XLenLLT?
XLenLLT is the only legal type on RISCV. 


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir:3
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
----------------
arsenm wrote:
> Need some < 8 bit and odd intermediate sizes too
This doesn't work with odd-sized types right now, I'll update the description and fix that in a future patch. 

I added one test for i1; but in order to pass it, I needed to change the legalization logic for G_{ANY/Z/S}EXT. Specifically, I allowed the SrcSize and DstSize to be as small as 1 for legal instructions. But neither X86 nor AArch64 allows this, so I'm not sure we should be allowing this.


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Comment at: llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir:21
+    %3:_(s8) = G_TRUNC %1(s32)
+    %4:_(s8) = G_ASHR %3, %4
+    %5:_(s32) = G_ANYEXT %4(s8)
----------------
tschuett wrote:
> Input and output are %4?
Thank you for catching this.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155772/new/

https://reviews.llvm.org/D155772