[PATCH] D156477: [RISCVRVVInitUndef] Remove implicit single use assumption for IMPLICIT_DEF

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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The code was written with the implicit assumption that each IMPLICIT_DEF either a) the tied operand, or b) an untied source, but not both.  This is true right now, but an upcoming change may allow CSE of IMPLICIT_DEFs in some cases, so let's rewrite the code to handle that possibility.

I added an MIR case which demonstrates the multiple use IMPLICIT_DEF.  To my knowledge, this is not a reachable configuration from IR right now.

As an aside, this makes the structure a much closer match with the sub-reg liveness case, and we can probably just merge these routines.  (Future work.)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156477

Files:
  llvm/lib/Target/RISCV/RISCVRVVInitUndef.cpp
  llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
  llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.mir

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