[PATCH] D156412: [AMDGPU] Callee saves for amdgpu_cs_chain[_preserve]

[Diana Picus via Phabricator via llvm-commits]

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Teach prolog epilog insertion how to handle functions with the
amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions.

For amdgpu_cs_chain functions, we only need to preserve the inactive
lanes of VGPRs above v8, and only in the presence of calls via
@llvm.amdgcn.cs.chain.

For amdgpu_cs_chain_preserve functions, we will also need to preserve
the active lanes for registers above the last argument VGPR. AFAICT
there's no direct way to find out what the last argument VGPR is, so
instead the patch uses the fact that chain calls from
amdgpu_cs_chain_preserve functions can't use more VGPRs than the
caller's VGPR arguments. In other words, it removes the operands of
SI_TCRETURN instructions from the list of callee saved registers.

For both calling conventions, registers v0-v7 never need to be saved and
restored, so we should never add them as WWM spills.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156412

Files:
  llvm/lib/Target/AMDGPU/AMDGPUCallingConv.td
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
  llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
  llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir

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