[PATCH] D156404: [RISCV] Use x0 in vsetvli when avl is equal to vlmax.

[Jianjian Guan via Phabricator via llvm-commits]

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We could use x0 form in vsetvli when we already know the vlmax and avl is equal to it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156404

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll


Index: llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
+++ llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
@@ -1,8 +1,14 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
-; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,VLENUNKONWN
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
-; RUN:   -verify-machineinstrs | FileCheck %s
+; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,VLENUNKONWN
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
+; RUN:   -riscv-v-vector-bits-max=128 -verify-machineinstrs \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,VLEN128
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
+; RUN:   -riscv-v-vector-bits-max=128 -verify-machineinstrs \
+; RUN:   | FileCheck %s --check-prefixes=CHECK,VLEN128
 
 declare iXLen @llvm.riscv.vsetvli.iXLen(iXLen, iXLen, iXLen)
 declare iXLen @llvm.riscv.vsetvlimax.iXLen(iXLen, iXLen)
@@ -135,3 +141,18 @@
   %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen -1, iXLen 0, iXLen 0)
   ret iXLen %vl
 }
+
+define iXLen @test_vsetvli_eqvlmax_e8m8(iXLen %avl) nounwind {
+; VLENUNKONWN-LABEL: test_vsetvli_eqvlmax_e8m8:
+; VLENUNKONWN:       # %bb.0:
+; VLENUNKONWN-NEXT:    li a0, 128
+; VLENUNKONWN-NEXT:    vsetvli a0, a0, e8, m8, ta, ma
+; VLENUNKONWN-NEXT:    ret
+;
+; VLEN128-LABEL: test_vsetvli_eqvlmax_e8m8:
+; VLEN128:       # %bb.0:
+; VLEN128-NEXT:    vsetvli a0, zero, e8, m8, ta, ma
+; VLEN128-NEXT:    ret
+  %vl = call iXLen @llvm.riscv.vsetvli.iXLen(iXLen 128, iXLen 0, iXLen 3)
+  ret iXLen %vl
+}
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -552,6 +552,13 @@
 
   SDValue VLOperand;
   unsigned Opcode = RISCV::PseudoVSETVLI;
+  if (auto *C = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
+    if (Subtarget->getRealMinVLen() == Subtarget->getRealMaxVLen()) {
+      const unsigned VLEN = Subtarget->getRealMinVLen();
+      if (VLEN / RISCVVType::getSEWLMULRatio(SEW, VLMul) == C->getZExtValue())
+        VLMax = true;
+    }
+  }
   if (VLMax || isAllOnesConstant(Node->getOperand(1))) {
     VLOperand = CurDAG->getRegister(RISCV::X0, XLenVT);
     Opcode = RISCV::PseudoVSETVLIX0;


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