[PATCH] D156396: [AArch64] Respect pre-/post-decrement indexing mode during instruction selection

[Maurice Heumann via Phabricator via llvm-commits]

momo5502 created this revision.
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Loads with pre-decrement and post-decrement indexing modes are lowered as pre-increment and post-increment loads on AArch64.
The decrement-semantics are ignored, which results in incorrect addressing.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D156396

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp


Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -1422,6 +1422,7 @@
   EVT DstVT = N->getValueType(0);
   ISD::MemIndexedMode AM = LD->getAddressingMode();
   bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
+  bool IsDec = AM == ISD::PRE_DEC || AM == ISD::POST_DEC;
 
   // We're not doing validity checking here. That was done when checking
   // if we should mark the load as indexed or not. We're just selecting
@@ -1486,6 +1487,7 @@
   SDValue Base = LD->getBasePtr();
   ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
   int OffsetVal = (int)OffsetOp->getZExtValue();
+  OffsetVal = IsDec ? -OffsetVal : OffsetVal;
   SDLoc dl(N);
   SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
   SDValue Ops[] = { Base, Offset, Chain };


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