[llvm] 25e1d61 - [RISCV] Correct policy operand for RVV ISel patterns with merge operand as implicit_def (NFC)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 26 22:17:21 PDT 2023
Author: eopXD
Date: 2023-07-26T22:17:16-07:00
New Revision: 25e1d61013b99fafc0441d34c3bdaab089199bea
URL: https://github.com/llvm/llvm-project/commit/25e1d61013b99fafc0441d34c3bdaab089199bea
DIFF: https://github.com/llvm/llvm-project/commit/25e1d61013b99fafc0441d34c3bdaab089199bea.diff
LOG: [RISCV] Correct policy operand for RVV ISel patterns with merge operand as implicit_def (NFC)
The trailing TU_MU suffixes was added in D154625. The trailing policy
operand for these patterns has no real affect, as the vsetvli insertion
pass omits the trailing policy operand when the merge operand is
undefined.
This patch is essentially an NFC. However, the policy implied for these
patterns is actually TA_MA. This patch corrects them to avoid confusion.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D156342
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 1479735ddc6ce2..c3e454cd3786f7 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -3734,7 +3734,7 @@ class VPatMaskUnaryNoMask<string intrinsic_name,
(!cast<Instruction>(inst#"_M_"#mti.BX)
(mti.Mask (IMPLICIT_DEF)),
(mti.Mask VR:$rs2),
- GPR:$vl, mti.Log2SEW, TU_MU)>;
+ GPR:$vl, mti.Log2SEW, TA_MA)>;
class VPatMaskUnaryMask<string intrinsic_name,
string inst,
@@ -5893,7 +5893,7 @@ foreach vti = AllIntegerVectors in {
vti.RegClass:$rs1,
(NegImm simm5_plus1:$rs2),
GPR:$vl,
- vti.Log2SEW, TU_MU)>;
+ vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (int_riscv_vsub_mask (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs1),
(vti.Scalar simm5_plus1:$rs2),
@@ -6552,7 +6552,7 @@ foreach vti = AllIntegerVectors in {
(XLenVT 1), VLOpFrag)),
(!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
- vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs1),
(XLenVT 1),
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 4141c7698bb408..603d220ff5f003 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -35,7 +35,7 @@ multiclass VPatUSLoadStoreSDNode<ValueType type,
// Load
def : Pat<(type (load GPR:$rs1)),
(load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl,
- log2sew, TU_MU)>;
+ log2sew, TA_MA)>;
// Store
def : Pat<(store type:$rs2, GPR:$rs1),
(store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
@@ -399,7 +399,7 @@ multiclass VPatExtendSDNode_V<list<SDNode> ops, string inst_name, string suffix,
def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))),
(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- fti.RegClass:$rs2, fti.AVL, vti.Log2SEW, TU_MU)>;
+ fti.RegClass:$rs2, fti.AVL, vti.Log2SEW, TA_MA)>;
}
}
@@ -416,7 +416,7 @@ multiclass VPatConvertI2FPSDNode_V_RM<SDPatternOperator vop,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- fvti.AVL, fvti.Log2SEW, TU_MU)>;
+ fvti.AVL, fvti.Log2SEW, TA_MA)>;
}
}
@@ -429,7 +429,7 @@ multiclass VPatConvertFP2ISDNode_V<SDPatternOperator vop,
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
(ivti.Vector (IMPLICIT_DEF)),
- fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW, TU_MU)>;
+ fvti.RegClass:$rs1, ivti.AVL, ivti.Log2SEW, TA_MA)>;
}
}
@@ -444,7 +444,7 @@ multiclass VPatWConvertI2FPSDNode_V<SDPatternOperator vop,
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
(fwti.Vector (IMPLICIT_DEF)),
ivti.RegClass:$rs1,
- ivti.AVL, ivti.Log2SEW, TU_MU)>;
+ ivti.AVL, ivti.Log2SEW, TA_MA)>;
}
}
@@ -458,7 +458,7 @@ multiclass VPatWConvertFP2ISDNode_V<SDPatternOperator vop,
def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
(iwti.Vector (IMPLICIT_DEF)),
- fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW, TU_MU)>;
+ fvti.RegClass:$rs1, fvti.AVL, fvti.Log2SEW, TA_MA)>;
}
}
@@ -476,7 +476,7 @@ multiclass VPatNConvertI2FPSDNode_W_RM<SDPatternOperator vop,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- fvti.AVL, fvti.Log2SEW, TU_MU)>;
+ fvti.AVL, fvti.Log2SEW, TA_MA)>;
}
}
@@ -490,7 +490,7 @@ multiclass VPatNConvertFP2ISDNode_W<SDPatternOperator vop,
def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1))),
(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
+ fwti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
@@ -505,12 +505,12 @@ multiclass VPatWidenBinarySDNode_VV_VX<SDNode op, PatFrags extop1, PatFrags exto
(wti.Vector (extop2 (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
- vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (extop2 (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
(!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
- GPR:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
+ GPR:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
}
@@ -531,7 +531,7 @@ multiclass VPatWidenBinarySDNode_WV_WX<SDNode op, PatFrags extop,
(wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2, GPR:$rs1,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
}
@@ -588,7 +588,7 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
- vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
@@ -597,14 +597,14 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF<SDNode op, string instruction_name> {
(vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
- vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
- vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
}
@@ -627,7 +627,7 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
@@ -640,7 +640,7 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))),
@@ -651,7 +651,7 @@ multiclass VPatWidenBinaryFPSDNode_VV_VF_RM<SDNode op, string instruction_name>
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
}
@@ -683,7 +683,7 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF_RM<SDNode op, string instruction_name>
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (SplatFPOp (fpext_oneuse (vti.Scalar vti.ScalarRegClass:$rs1))))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
@@ -692,7 +692,7 @@ multiclass VPatWidenBinaryFPSDNode_WV_WF_RM<SDNode op, string instruction_name>
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
}
@@ -916,12 +916,12 @@ foreach vti = AllIntegerVectors in {
(vti.Vector vti.RegClass:$rs1)),
(!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)),
(vti.Vector vti.RegClass:$rs1)),
(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
- simm5:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
+ simm5:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
@@ -944,17 +944,17 @@ foreach vtiToWti = AllWidenableIntVectors in {
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs1,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs1,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(shl (wti.Vector (anyext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX)
(wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs1,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
@@ -989,7 +989,7 @@ foreach vti = AllIntegerVectors in {
(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
- vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TA_MA)>;
}
@@ -1279,40 +1279,40 @@ foreach vti = AllFloatVectors in {
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.AVL, vti.Log2SEW, TA_MA)>;
// 13.12. Vector Floating-Point Sign-Injection Instructions
def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),
(!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;
// Handle fneg with VFSGNJN using the same input for both operands.
def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))),
(!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (fneg vti.RegClass:$rs2)))),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))),
(!cast<Instruction>("PseudoVFSGNJN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TA_MA)>;
}
}
@@ -1392,7 +1392,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
- fvti.AVL, fvti.Log2SEW, TU_MU)>;
+ fvti.AVL, fvti.Log2SEW, TA_MA)>;
}
//===----------------------------------------------------------------------===//
@@ -1405,12 +1405,12 @@ foreach fvti = AllFloatVectors in {
(!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
(fvti.Vector (IMPLICIT_DEF)),
(fvti.Scalar fvti.ScalarRegClass:$rs1),
- fvti.AVL, fvti.Log2SEW, TU_MU)>;
+ fvti.AVL, fvti.Log2SEW, TA_MA)>;
def : Pat<(fvti.Vector (SplatFPOp (fvti.Scalar fpimm0))),
(!cast<Instruction>("PseudoVMV_V_I_"#fvti.LMul.MX)
(fvti.Vector (IMPLICIT_DEF)),
- 0, fvti.AVL, fvti.Log2SEW, TU_MU)>;
+ 0, fvti.AVL, fvti.Log2SEW, TA_MA)>;
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 90b863318b3397..bd48e7b50e6792 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1449,7 +1449,7 @@ multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> {
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;
def : Pat<
(vti.Vector
@@ -1460,7 +1460,7 @@ multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> {
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;
def : Pat<
(vti.Vector
@@ -1470,7 +1470,7 @@ multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> {
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}
}
@@ -1695,7 +1695,7 @@ multiclass VPatNarrowShiftSplatExt_WX<SDNode op, PatFrags extop, string instruct
(vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}
@@ -1715,7 +1715,7 @@ multiclass VPatNarrowShiftExtVL_WV<SDNode op, PatFrags extop, string instruction
(vti.Mask V0), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2, vti.RegClass:$rs1,
- (vti.Mask V0), GPR:$vl, vti.Log2SEW, TU_MU)>;
+ (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}
@@ -1834,13 +1834,13 @@ multiclass VPatNarrowShiftSplat_WX_WI<SDNode op, string instruction_name> {
srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (riscv_trunc_vector_vl
(wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2),
srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}
}
@@ -2134,7 +2134,7 @@ foreach vti = AllIntegerVectors in {
srcvalue, (vti.Mask true_mask), VLOpFrag),
(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TA_MA)>;
}
// 11.7. Vector Narrowing Integer Right Shift Instructions
@@ -2443,7 +2443,7 @@ foreach vti = AllFloatVectors in {
VLOpFrag),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
- vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;
def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),
(SplatFPOp vti.ScalarRegClass:$rs2),
@@ -2466,7 +2466,7 @@ foreach vti = AllFloatVectors in {
def : Pat<(riscv_fclass_vl (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), VLOpFrag),
(!cast<Instruction>("PseudoVFCLASS_V_"# vti.LMul.MX)
- (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}
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