[PATCH] D156381: Revert "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"

Vitaly Buka via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jul 26 22:14:01 PDT 2023 

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa496c8be6e63: Revert "[CodeGen]Allow targets to use target specific COPY instructions for… (authored by vitalybuka).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156381/new/

https://reviews.llvm.org/D156381

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/CalcSpillWeights.cpp
  llvm/lib/CodeGen/InlineSpiller.cpp
  llvm/lib/CodeGen/LiveRangeEdit.cpp
  llvm/lib/CodeGen/LiveRangeShrink.cpp
  llvm/lib/CodeGen/RegAllocGreedy.cpp
  llvm/lib/CodeGen/SplitKit.cpp
  llvm/lib/CodeGen/SplitKit.h
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/AMDGPU/AMDGPU.h
  llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
  llvm/lib/Target/AMDGPU/CMakeLists.txt
  llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.h
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
  llvm/lib/Target/AMDGPU/SILowerWWMCopies.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
  llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/GlobalISel/assert-align.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/image-waterfall-loop-O0.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll
  llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
  llvm/test/CodeGen/AMDGPU/amdpal-callable.ll
  llvm/test/CodeGen/AMDGPU/bf16.ll
  llvm/test/CodeGen/AMDGPU/call-alias-register-usage-agpr.ll
  llvm/test/CodeGen/AMDGPU/call-alias-register-usage0.ll
  llvm/test/CodeGen/AMDGPU/call-alias-register-usage1.ll
  llvm/test/CodeGen/AMDGPU/call-alias-register-usage2.ll
  llvm/test/CodeGen/AMDGPU/call-alias-register-usage3.ll
  llvm/test/CodeGen/AMDGPU/call-argument-types.ll
  llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
  llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
  llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
  llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
  llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
  llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
  llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
  llvm/test/CodeGen/AMDGPU/extend-wwm-virt-reg-liveness.mir
  llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll
  llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
  llvm/test/CodeGen/AMDGPU/fold-reload-into-exec.mir
  llvm/test/CodeGen/AMDGPU/fold-reload-into-m0.mir
  llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
  llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
  llvm/test/CodeGen/AMDGPU/indirect-call.ll
  llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll
  llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
  llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
  llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
  llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
  llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/nested-calls.ll
  llvm/test/CodeGen/AMDGPU/no-source-locations-in-prologue.ll
  llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
  llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
  llvm/test/CodeGen/AMDGPU/scc-clobbered-sgpr-to-vmem-spill.ll
  llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-dead-frame-in-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-fi-skip-processing-stack-arg-dbg-value.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-partially-undef.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spill-update-only-slot-indexes.ll
  llvm/test/CodeGen/AMDGPU/sgpr-spill-vmem-large-frame.mir
  llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
  llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
  llvm/test/CodeGen/AMDGPU/sibling-call.ll
  llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir
  llvm/test/CodeGen/AMDGPU/spill-csr-frame-ptr-reg-copy.ll
  llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
  llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
  llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr-update-regscavenger.ll
  llvm/test/CodeGen/AMDGPU/spill-writelane-vgprs.ll
  llvm/test/CodeGen/AMDGPU/spill192.mir
  llvm/test/CodeGen/AMDGPU/spill224.mir
  llvm/test/CodeGen/AMDGPU/spill288.mir
  llvm/test/CodeGen/AMDGPU/spill320.mir
  llvm/test/CodeGen/AMDGPU/spill352.mir
  llvm/test/CodeGen/AMDGPU/spill384.mir
  llvm/test/CodeGen/AMDGPU/stack-realign.ll
  llvm/test/CodeGen/AMDGPU/swdev380865.ll
  llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
  llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
  llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
  llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
  llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
  llvm/test/CodeGen/AMDGPU/wave32.ll
  llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
  llvm/test/CodeGen/AMDGPU/whole-wave-register-spill.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
  llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
  llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
  llvm/test/CodeGen/Mips/madd-msub.ll
  llvm/test/CodeGen/X86/GlobalISel/add-ext.ll
  llvm/test/CodeGen/X86/dagcombine-cse.ll
  llvm/test/CodeGen/X86/fold-and-shift-x86_64.ll
  llvm/test/CodeGen/X86/unfold-masked-merge-scalar-constmask-lowhigh.ll

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