[PATCH] D155916: [RISCV] Remove some instructions from Zvfbfwma by implying Zfbfmin according to the latest spec

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Support/RISCVISAInfo.cpp:985
+static const char *ImpliedExtsZvfbfmin[] = {"zve32f", "zfbfmin"};
+static const char *ImpliedExtsZvfbfwma[] = {"zve32f", "zvfbfmin"};
 static const char *ImpliedExtsZvfh[] = {"zve32f", "zfhmin"};
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You can drop zve32f here now since its in Zvfbfmin


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Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:467
                        "'Zvbfmin' (Vector BF16 Converts)",
                        [FeatureStdExtZve32f]>;
 def HasStdExtZvfbfmin : Predicate<"Subtarget->hasStdExtZvfbfmin()">,
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Need to add Zfbfmin here?


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Comment at: llvm/lib/Target/RISCV/RISCVFeatures.td:475
                        "'Zvfbfwma' (Vector BF16 widening mul-add)",
                        [FeatureStdExtZve32f]>;
 def HasStdExtZvfbfwma : Predicate<"Subtarget->hasStdExtZvfbfwma()">,
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I think we need to add Zvfbfmin here


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155916/new/

https://reviews.llvm.org/D155916