[PATCH] D156390: [SDAG][RISCV] Avoid expanding is-power-of-2 pattern on riscv32/64 with zbb

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:17502
+  if (VT.isVector())
+    return isTypeLegal(VT) && Subtarget.hasStdExtZvbb();
+  return Subtarget.hasStdExtZbb() && (VT == MVT::i32 || VT == MVT::i64);
----------------
The vector part of this isn't tested.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156390/new/

https://reviews.llvm.org/D156390