[PATCH] D155928: [RISCV] Add patterns for vnsrl.vx where shift amount is truncated
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 26 12:27:03 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
luke marked an inline comment as done.
Closed by commit rGce8f094da8b2: [RISCV] Add patterns for vnsrl.vx where shift amount is truncated (authored by luke).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155928/new/
https://reviews.llvm.org/D155928
Files:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll
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