[PATCH] D156345: RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG

[Matt Arsenault via Phabricator via llvm-commits]

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Currently coalescing with SUBREG_TO_REG introduces an invisible load
bearing undef. There is liveness for the super register not
represented in the MIR.

      

This is part 1 of a fix for regressions that appeared after
b7836d856206ec39509d42529f958c920368166b <https://reviews.llvm.org/rGb7836d856206ec39509d42529f958c920368166b>. The allocator started
recognizing undef-def subregister MOVs as copies. Since there was no
representation for the dependency on the high bits, different undef
segments of the super register ended up disconnected and downstream
users ended up observing different undefs than they did previously.

      

This does not yet fix the regression. The isCopyInstr handling needs
to start handling implicit-defs on any instruction.

      

I wanted to include an end to end IR test since the actual failure
only appeared with an interaction between the coalescer and the
allocator. It's a bit bigger than I'd like but I'm having a bit of
trouble reducing it to something which definitely shows a diff that's
meaningful.

      

The same problem likely exists everywhere trying to do anything with
SUBREG_TO_REG. I don't understand how this managed to be broken for so
long.

      

This needs to be applied to the release branch.


https://reviews.llvm.org/D156345

Files:
  llvm/lib/CodeGen/RegisterCoalescer.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
  llvm/test/CodeGen/X86/bswap.ll
  llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness-reduced.ll
  llvm/test/CodeGen/X86/coalescer-breaks-subreg-to-reg-liveness.ll
  llvm/test/CodeGen/X86/subreg-to-reg-coalescing.mir

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