[PATCH] D138809: [RISCV] Support vector crypto extension LLVM IR

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1551
       return selectVSETVLI(Node);
+    case Intrinsic::riscv_vrol: {
+      SDValue Merge = Node->getOperand(1);
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This seems unnecessarily complex. https://reviews.llvm.org/D155439 already did this for non-intrinsics using an SDNodeXForm in tablegen


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7121
 
+// EGW should be greater than or equal to EGS * SEW
+static inline bool isValidEGW(int EGS, EVT VT) {
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This is dead code in release builds and will give a build warning.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:7261
+  case Intrinsic::riscv_vsm4r_vs: {
+    assert(isValidEGW(4, Op.getSimpleValueType()) &&
+           isValidEGW(4, Op->getOperand(1).getSimpleValueType()) &&
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This assert isn't helpful to compiler users. It's not part of release builds.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138809/new/

https://reviews.llvm.org/D138809