[llvm] cdffaac - [RISCV] Add Zbs instructions to SiFive7 SchedModel

[Michael Maitland via llvm-commits]

Author: Michael Maitland
Date: 2023-07-25T19:54:17-07:00
New Revision: cdffaac6ad2e0f9fcbe0ee75a5d3d78fea91cfa5

URL: https://github.com/llvm/llvm-project/commit/cdffaac6ad2e0f9fcbe0ee75a5d3d78fea91cfa5
DIFF: https://github.com/llvm/llvm-project/commit/cdffaac6ad2e0f9fcbe0ee75a5d3d78fea91cfa5.diff

LOG: [RISCV] Add Zbs instructions to SiFive7 SchedModel

BEXT[I] is available on A and B pipes, and has single-cycle latency. The other
instructions are only available on B-pipe, but otherwise have single-cycle
latency.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index e22c05b30b7faa..466a788b1278a6 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -292,6 +292,16 @@ def : WriteRes<WriteSHXADD, [SiFive7PipeB]>;
 def : WriteRes<WriteSHXADD32, [SiFive7PipeB]>;
 }
 
+// Single-bit instructions
+// BEXT[I] instruction is available on all ALUs and the other instructions
+// are only available on the SiFive7B pipe.
+let Latency = 3 in {
+def : WriteRes<WriteSingleBit, [SiFive7PipeB]>;
+def : WriteRes<WriteSingleBitImm, [SiFive7PipeB]>;
+def : WriteRes<WriteBEXT, [SiFive7PipeAB]>;
+def : WriteRes<WriteBEXTI, [SiFive7PipeAB]>;
+}
+
 // Memory
 def : WriteRes<WriteSTB, [SiFive7PipeA]>;
 def : WriteRes<WriteSTH, [SiFive7PipeA]>;
@@ -987,6 +997,9 @@ def : SiFive7AnyToGPRBypass<ReadORCB>;
 def : SiFive7AnyToGPRBypass<ReadREV8>;
 def : SiFive7AnyToGPRBypass<ReadSHXADD>;
 def : SiFive7AnyToGPRBypass<ReadSHXADD32>;
+// Single-bit instructions
+def : SiFive7AnyToGPRBypass<ReadSingleBit>;
+def : SiFive7AnyToGPRBypass<ReadSingleBitImm>;
 
 // 6. Configuration-Setting Instructions
 def : ReadAdvance<ReadVSETVLI, 2>;
@@ -1158,7 +1171,6 @@ def : ReadAdvance<ReadVMask, 0>;
 //===----------------------------------------------------------------------===//
 // Unsupported extensions
 defm : UnsupportedSchedZbc;
-defm : UnsupportedSchedZbs;
 defm : UnsupportedSchedZbkb;
 defm : UnsupportedSchedZbkx;
 defm : UnsupportedSchedZfa;