[PATCH] D153748: [RISCV] Add support for XCValu extension in CV32E40P

Tue Jul 25 15:43:36 PDT 2023

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM

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Comment at: llvm/docs/RISCVUsage.rst:277
+
+``XCValu``
+  LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/4f024fe4b15a68b76615b0630c07a6745c620da7/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time.
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Keep this with the other XCV extensions

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153748/new/

https://reviews.llvm.org/D153748