[PATCH] D156258: [WIP][RISCV] Exploring directions for vector mem* lowering

[Philip Reames via Phabricator via llvm-commits]

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Highly experimental, not for review!

This is a follow up to D156249 <https://reviews.llvm.org/D156249> exploring a few ideas for how we might leverage VL predication in mem* lowering.  At the moment, this is purely a discussion piece.  I wanted to see what was easily possible, and than bounce around various approaches.  It's not clear to me that any of these are clearly profitable (in general).


https://reviews.llvm.org/D156258

Files:
  llvm/include/llvm/CodeGen/TargetLowering.h
  llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64ISelLowering.h
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.h
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/lib/Target/ARM/ARMISelLowering.h
  llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
  llvm/lib/Target/BPF/BPFISelLowering.h
  llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
  llvm/lib/Target/Hexagon/HexagonISelLowering.h
  llvm/lib/Target/Mips/MipsISelLowering.cpp
  llvm/lib/Target/Mips/MipsISelLowering.h
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.h
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
  llvm/lib/Target/SystemZ/SystemZISelLowering.h
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/RISCV/rvv/memcpy-inline.ll
  llvm/test/CodeGen/RISCV/rvv/memset-inline.ll

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