[llvm] 76c22b1 - [FPEnv][AMDGPU] Correct strictfp tests.
Kevin P. Neal via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 25 10:24:55 PDT 2023
Author: Kevin P. Neal
Date: 2023-07-25T13:24:46-04:00
New Revision: 76c22b18eafd2156568d72e9df2ff7bd3457888a
URL: https://github.com/llvm/llvm-project/commit/76c22b18eafd2156568d72e9df2ff7bd3457888a
DIFF: https://github.com/llvm/llvm-project/commit/76c22b18eafd2156568d72e9df2ff7bd3457888a.diff
LOG: [FPEnv][AMDGPU] Correct strictfp tests.
Correct AMDGPU strictfp tests to follow the rules documented in the LangRef:
https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics
Mostly these tests just needed the strictfp attribute on function
definitions. I've also removed the strictfp attribute from uses
of the constrained intrinsics because it comes by default since
D154991, but I only did this in tests I was changing anyway.
I also removed attributes added to declare lines of intrinsics. The
attributes of intrinsics cannot be changed in a test so I eliminated
attempts to do so.
Test changes verified with D146845.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
index ccbf128f0f4758..15740ee5476e84 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
@@ -117,8 +117,8 @@ define half @v_constained_fma_f16_fpexcept_strict_fabs_fabs(half %x, half %y, ha
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_fma_f16 v0, |v0|, |v1|, v2
; GCN-NEXT: s_setpc_b64 s[30:31]
- %neg.x = call half @llvm.fabs.f16(half %x)
- %neg.y = call half @llvm.fabs.f16(half %y)
+ %neg.x = call half @llvm.fabs.f16(half %x) #0
+ %neg.y = call half @llvm.fabs.f16(half %y) #0
%val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret half %val
}
@@ -149,11 +149,10 @@ define <2 x half> @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg(<2 x half> %
ret <2 x half> %val
}
-declare half @llvm.fabs.f16(half) #1
-declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1
-declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata) #1
-declare <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half>, <3 x half>, <3 x half>, metadata, metadata) #1
-declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1
+declare half @llvm.fabs.f16(half)
+declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata)
+declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata)
+declare <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half>, <3 x half>, <3 x half>, metadata, metadata)
+declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
index 5c36ef18724ad4..5955c590e9d1cb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f32.ll
@@ -76,8 +76,8 @@ define float @v_constained_fma_f32_fpexcept_strict_fabs_fabs(float %x, float %y,
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_fma_f32 v0, |v0|, |v1|, v2
; GCN-NEXT: s_setpc_b64 s[30:31]
- %neg.x = call float @llvm.fabs.f32(float %x)
- %neg.y = call float @llvm.fabs.f32(float %y)
+ %neg.x = call float @llvm.fabs.f32(float %x) #0
+ %neg.y = call float @llvm.fabs.f32(float %y) #0
%val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -95,11 +95,10 @@ define <2 x float> @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg(<2 x float>
ret <2 x float> %val
}
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
-declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata) #1
-declare <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float>, <3 x float>, <3 x float>, metadata, metadata) #1
-declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata) #1
+declare float @llvm.fabs.f32(float)
+declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float>, <3 x float>, <3 x float>, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
index 0c11e8fe465f96..04a07c42c934c6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f64.ll
@@ -76,8 +76,8 @@ define double @v_constained_fma_f64_fpexcept_strict_fabs_fabs(double %x, double
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_fma_f64 v[0:1], |v[0:1]|, |v[2:3]|, v[4:5]
; GCN-NEXT: s_setpc_b64 s[30:31]
- %neg.x = call double @llvm.fabs.f64(double %x)
- %neg.y = call double @llvm.fabs.f64(double %y)
+ %neg.x = call double @llvm.fabs.f64(double %x) #0
+ %neg.y = call double @llvm.fabs.f64(double %y) #0
%val = call double @llvm.experimental.constrained.fma.f64(double %neg.x, double %neg.y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret double %val
}
@@ -95,11 +95,10 @@ define <2 x double> @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg(<2 x doubl
ret <2 x double> %val
}
-declare double @llvm.fabs.f64(double) #1
-declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1
-declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1
-declare <3 x double> @llvm.experimental.constrained.fma.v3f64(<3 x double>, <3 x double>, <3 x double>, metadata, metadata) #1
-declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata) #1
+declare double @llvm.fabs.f64(double)
+declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)
+declare <3 x double> @llvm.experimental.constrained.fma.v3f64(<3 x double>, <3 x double>, <3 x double>, metadata, metadata)
+declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
index 23c97c9bf17521..ab84d8a3725ae4 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
@@ -1388,7 +1388,7 @@ define i1 @isnan_f16_strictfp(half %x) strictfp nounwind {
; GFX11CHECK-NEXT: v_cmp_class_f16_e64 s0, v0, 3
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
- %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) ; nan
+ %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3) strictfp ; nan
ret i1 %1
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
index ab79bfeb67ae33..638be76bf65786 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.ll
@@ -1060,7 +1060,7 @@ define i1 @isnan_f32_strictfp(float %x) strictfp nounwind {
; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
- %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan
+ %1 = call i1 @llvm.is.fpclass.f32(float %x, i32 3) strictfp ; nan
ret i1 %1
}
@@ -1100,7 +1100,7 @@ define i1 @isnan_f64_strictfp(double %x) strictfp nounwind {
; GFX11CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX11CHECK-NEXT: s_setpc_b64 s[30:31]
- %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) ; nan
+ %1 = call i1 @llvm.is.fpclass.f64(double %x, i32 3) strictfp ; nan
ret i1 %1
}
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
index 5b81093ca5e811..2aecf5fd8753c9 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll
@@ -177,7 +177,7 @@ define float @v_constained_fadd_f32_fpexcept_strict_fabs_lhs(float %x, float %y)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_add_f32_e64 v0, |v0|, v1
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.x = call float @llvm.fabs.f32(float %x)
+ %fabs.x = call float @llvm.fabs.f32(float %x) #0
%val = call float @llvm.experimental.constrained.fadd.f32(float %fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -194,7 +194,7 @@ define float @v_constained_fadd_f32_fpexcept_strict_fabs_rhs(float %x, float %y)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_add_f32_e64 v0, v0, |v1|
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.y = call float @llvm.fabs.f32(float %y)
+ %fabs.y = call float @llvm.fabs.f32(float %y) #0
%val = call float @llvm.experimental.constrained.fadd.f32(float %x, float %fabs.y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -211,16 +211,15 @@ define float @v_constained_fadd_f32_fpexcept_strict_fneg_fabs_lhs(float %x, floa
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_sub_f32_e64 v0, v1, |v0|
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.x = call float @llvm.fabs.f32(float %x)
+ %fabs.x = call float @llvm.fabs.f32(float %x) #0
%neg.fabs.x = fneg float %fabs.x
%val = call float @llvm.experimental.constrained.fadd.f32(float %neg.fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) #1
-declare <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float>, <2 x float>, metadata, metadata) #1
-declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, metadata) #1
+declare float @llvm.fabs.f32(float)
+declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float>, <2 x float>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
index 555798751821f1..407bb002483ec8 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll
@@ -238,8 +238,8 @@ define half @v_constained_fma_f16_fpexcept_strict_fabs_fabs(half %x, half %y, ha
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_fma_f16 v0, |v0|, |v1|, v2
; GFX11-NEXT: s_setpc_b64 s[30:31]
- %neg.x = call half @llvm.fabs.f16(half %x)
- %neg.y = call half @llvm.fabs.f16(half %y)
+ %neg.x = call half @llvm.fabs.f16(half %x) #0
+ %neg.y = call half @llvm.fabs.f16(half %y) #0
%val = call half @llvm.experimental.constrained.fma.f16(half %neg.x, half %neg.y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret half %val
}
@@ -280,11 +280,10 @@ define <2 x half> @v_constained_fma_v2f16_fpexcept_strict_fneg_fneg(<2 x half> %
ret <2 x half> %val
}
-declare half @llvm.fabs.f16(half) #1
-declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) #1
-declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata) #1
-declare <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half>, <3 x half>, <3 x half>, metadata, metadata) #1
-declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata) #1
+declare half @llvm.fabs.f16(half)
+declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata)
+declare <2 x half> @llvm.experimental.constrained.fma.v2f16(<2 x half>, <2 x half>, <2 x half>, metadata, metadata)
+declare <3 x half> @llvm.experimental.constrained.fma.v3f16(<3 x half>, <3 x half>, <3 x half>, metadata, metadata)
+declare <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half>, <4 x half>, <4 x half>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
index 6150515a1b7a40..922a4dcbea351e 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll
@@ -126,8 +126,8 @@ define float @v_constained_fma_f32_fpexcept_strict_fabs_fabs(float %x, float %y,
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_fma_f32 v0, |v0|, |v1|, v2
; GFX10-NEXT: s_setpc_b64 s[30:31]
- %neg.x = call float @llvm.fabs.f32(float %x)
- %neg.y = call float @llvm.fabs.f32(float %y)
+ %neg.x = call float @llvm.fabs.f32(float %x) #0
+ %neg.y = call float @llvm.fabs.f32(float %y) #0
%val = call float @llvm.experimental.constrained.fma.f32(float %neg.x, float %neg.y, float %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -152,11 +152,10 @@ define <2 x float> @v_constained_fma_v2f32_fpexcept_strict_fneg_fneg(<2 x float>
ret <2 x float> %val
}
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
-declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata) #1
-declare <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float>, <3 x float>, <3 x float>, metadata, metadata) #1
-declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata) #1
+declare float @llvm.fabs.f32(float)
+declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.fma.v3f32(<3 x float>, <3 x float>, <3 x float>, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
index d52b157f202f70..5cb293ab25806a 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll
@@ -126,8 +126,8 @@ define double @v_constained_fma_f64_fpexcept_strict_fabs_fabs(double %x, double
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: v_fma_f64 v[0:1], |v[0:1]|, |v[2:3]|, v[4:5]
; GFX10-NEXT: s_setpc_b64 s[30:31]
- %neg.x = call double @llvm.fabs.f64(double %x)
- %neg.y = call double @llvm.fabs.f64(double %y)
+ %neg.x = call double @llvm.fabs.f64(double %x) #0
+ %neg.y = call double @llvm.fabs.f64(double %y) #0
%val = call double @llvm.experimental.constrained.fma.f64(double %neg.x, double %neg.y, double %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret double %val
}
@@ -152,11 +152,10 @@ define <2 x double> @v_constained_fma_v2f64_fpexcept_strict_fneg_fneg(<2 x doubl
ret <2 x double> %val
}
-declare double @llvm.fabs.f64(double) #1
-declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata) #1
-declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata) #1
-declare <3 x double> @llvm.experimental.constrained.fma.v3f64(<3 x double>, <3 x double>, <3 x double>, metadata, metadata) #1
-declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata) #1
+declare double @llvm.fabs.f64(double)
+declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)
+declare <3 x double> @llvm.experimental.constrained.fma.v3f64(<3 x double>, <3 x double>, <3 x double>, metadata, metadata)
+declare <4 x double> @llvm.experimental.constrained.fma.v4f64(<4 x double>, <4 x double>, <4 x double>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
index 9c1c677d37f416..8df2834928395c 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll
@@ -180,7 +180,7 @@ define float @v_constained_fmul_f32_fpexcept_strict_fabs_lhs(float %x, float %y)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_mul_f32_e64 v0, |v0|, v1
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.x = call float @llvm.fabs.f32(float %x)
+ %fabs.x = call float @llvm.fabs.f32(float %x) #0
%val = call float @llvm.experimental.constrained.fmul.f32(float %fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -197,7 +197,7 @@ define float @v_constained_fmul_f32_fpexcept_strict_fabs_rhs(float %x, float %y)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_mul_f32_e64 v0, v0, |v1|
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.y = call float @llvm.fabs.f32(float %y)
+ %fabs.y = call float @llvm.fabs.f32(float %y) #0
%val = call float @llvm.experimental.constrained.fmul.f32(float %x, float %fabs.y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -214,16 +214,15 @@ define float @v_constained_fmul_f32_fpexcept_strict_fneg_fabs_lhs(float %x, floa
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_mul_f32_e64 v0, -|v0|, v1
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.x = call float @llvm.fabs.f32(float %x)
+ %fabs.x = call float @llvm.fabs.f32(float %x) #0
%neg.fabs.x = fneg float %fabs.x
%val = call float @llvm.experimental.constrained.fmul.f32(float %neg.fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) #1
-declare <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float>, <2 x float>, metadata, metadata) #1
-declare <3 x float> @llvm.experimental.constrained.fmul.v3f32(<3 x float>, <3 x float>, metadata, metadata) #1
+declare float @llvm.fabs.f32(float)
+declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.fmul.v2f32(<2 x float>, <2 x float>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.fmul.v3f32(<3 x float>, <3 x float>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
index 0a8bd4b96ffb10..23dbe21379f7ff 100644
--- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll
@@ -182,7 +182,7 @@ define float @v_constained_fsub_f32_fpexcept_strict_fabs_lhs(float %x, float %y)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_sub_f32_e64 v0, |v0|, v1
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.x = call float @llvm.fabs.f32(float %x)
+ %fabs.x = call float @llvm.fabs.f32(float %x) #0
%val = call float @llvm.experimental.constrained.fsub.f32(float %fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -199,7 +199,7 @@ define float @v_constained_fsub_f32_fpexcept_strict_fabs_rhs(float %x, float %y)
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_sub_f32_e64 v0, v0, |v1|
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.y = call float @llvm.fabs.f32(float %y)
+ %fabs.y = call float @llvm.fabs.f32(float %y) #0
%val = call float @llvm.experimental.constrained.fsub.f32(float %x, float %fabs.y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
@@ -216,16 +216,15 @@ define float @v_constained_fsub_f32_fpexcept_strict_fneg_fabs_lhs(float %x, floa
; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10PLUS-NEXT: v_sub_f32_e64 v0, -|v0|, v1
; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
- %fabs.x = call float @llvm.fabs.f32(float %x)
+ %fabs.x = call float @llvm.fabs.f32(float %x) #0
%neg.fabs.x = fneg float %fabs.x
%val = call float @llvm.experimental.constrained.fsub.f32(float %neg.fabs.x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
ret float %val
}
-declare float @llvm.fabs.f32(float) #1
-declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata) #1
-declare <2 x float> @llvm.experimental.constrained.fsub.v2f32(<2 x float>, <2 x float>, metadata, metadata) #1
-declare <3 x float> @llvm.experimental.constrained.fsub.v3f32(<3 x float>, <3 x float>, metadata, metadata) #1
+declare float @llvm.fabs.f32(float)
+declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
+declare <2 x float> @llvm.experimental.constrained.fsub.v2f32(<2 x float>, <2 x float>, metadata, metadata)
+declare <3 x float> @llvm.experimental.constrained.fsub.v3f32(<3 x float>, <3 x float>, metadata, metadata)
attributes #0 = { strictfp }
-attributes #1 = { inaccessiblememonly nounwind willreturn }
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