[llvm] 5ff5dac - [RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 25 09:03:51 PDT 2023
Author: Craig Topper
Date: 2023-07-25T09:03:45-07:00
New Revision: 5ff5dac8528ac23a006a1cec250e338c1185499a
URL: https://github.com/llvm/llvm-project/commit/5ff5dac8528ac23a006a1cec250e338c1185499a
DIFF: https://github.com/llvm/llvm-project/commit/5ff5dac8528ac23a006a1cec250e338c1185499a.diff
LOG: [RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
If we're selecting the result of two setccs that have been legalized
by introducing an xor with 1, we can pull the xor with 1 through the
select to enable more optimizations.
We could generalize this to other binary operators with identical
conditions, but those are usually caught before we legalize the select.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D156144
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/atomic-rmw.ll
llvm/test/CodeGen/RISCV/atomic-signext.ll
llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
llvm/test/CodeGen/RISCV/condops.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f49c5011607f99..4fd3caf52a0069 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -12933,6 +12933,19 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
}
}
+ // If both true/false are an xor with 1, pull through the select.
+ // This can occur after op legalization if both operands are setccs that
+ // require an xor to invert.
+ // FIXME: Generalize to other binary ops with identical operand?
+ if (TrueV.getOpcode() == ISD::XOR && FalseV.getOpcode() == ISD::XOR &&
+ TrueV.getOperand(1) == FalseV.getOperand(1) &&
+ isOneConstant(TrueV.getOperand(1)) &&
+ TrueV.hasOneUse() && FalseV.hasOneUse()) {
+ SDValue NewSel = DAG.getNode(RISCVISD::SELECT_CC, DL, VT, LHS, RHS, CC,
+ TrueV.getOperand(0), FalseV.getOperand(0));
+ return DAG.getNode(ISD::XOR, DL, VT, NewSel, TrueV.getOperand(1));
+ }
+
return SDValue();
}
case RISCVISD::BR_CC: {
diff --git a/llvm/test/CodeGen/RISCV/atomic-rmw.ll b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
index aabbb912bdafe4..ec27046bf7d08f 100644
--- a/llvm/test/CodeGen/RISCV/atomic-rmw.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-rmw.ll
@@ -15019,10 +15019,9 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB205_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB205_1
+; RV32I-NEXT: beqz a0, .LBB205_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -15074,10 +15073,9 @@ define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB205_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB205_1
+; RV32IA-NEXT: beqz a0, .LBB205_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB205_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -15174,10 +15172,9 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB206_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB206_1
+; RV32I-NEXT: beqz a0, .LBB206_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -15229,10 +15226,9 @@ define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB206_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB206_1
+; RV32IA-NEXT: beqz a0, .LBB206_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB206_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -15329,10 +15325,9 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB207_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB207_1
+; RV32I-NEXT: beqz a0, .LBB207_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -15384,10 +15379,9 @@ define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB207_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB207_1
+; RV32IA-NEXT: beqz a0, .LBB207_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB207_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -15484,10 +15478,9 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB208_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB208_1
+; RV32I-NEXT: beqz a0, .LBB208_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -15539,10 +15532,9 @@ define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB208_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB208_1
+; RV32IA-NEXT: beqz a0, .LBB208_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB208_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -15639,10 +15631,9 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB209_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB209_1
+; RV32I-NEXT: beqz a0, .LBB209_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -15694,10 +15685,9 @@ define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB209_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB209_1
+; RV32IA-NEXT: beqz a0, .LBB209_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB209_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -16559,10 +16549,9 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB215_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB215_1
+; RV32I-NEXT: beqz a0, .LBB215_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -16614,10 +16603,9 @@ define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB215_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB215_1
+; RV32IA-NEXT: beqz a0, .LBB215_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB215_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -16714,10 +16702,9 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB216_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB216_1
+; RV32I-NEXT: beqz a0, .LBB216_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -16769,10 +16756,9 @@ define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB216_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB216_1
+; RV32IA-NEXT: beqz a0, .LBB216_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB216_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -16869,10 +16855,9 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB217_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB217_1
+; RV32I-NEXT: beqz a0, .LBB217_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -16924,10 +16909,9 @@ define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB217_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB217_1
+; RV32IA-NEXT: beqz a0, .LBB217_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB217_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -17024,10 +17008,9 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB218_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB218_1
+; RV32I-NEXT: beqz a0, .LBB218_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -17079,10 +17062,9 @@ define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB218_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB218_1
+; RV32IA-NEXT: beqz a0, .LBB218_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB218_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -17179,10 +17161,9 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB219_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB219_1
+; RV32I-NEXT: beqz a0, .LBB219_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -17234,10 +17215,9 @@ define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB219_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB219_1
+; RV32IA-NEXT: beqz a0, .LBB219_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB219_2 Depth=1
; RV32IA-NEXT: mv a2, s2
diff --git a/llvm/test/CodeGen/RISCV/atomic-signext.ll b/llvm/test/CodeGen/RISCV/atomic-signext.ll
index 48fce214905929..c08f045ee8abc0 100644
--- a/llvm/test/CodeGen/RISCV/atomic-signext.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-signext.ll
@@ -3318,10 +3318,9 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB44_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB44_1
+; RV32I-NEXT: beqz a0, .LBB44_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -3373,10 +3372,9 @@ define signext i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB44_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB44_1
+; RV32IA-NEXT: beqz a0, .LBB44_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB44_2 Depth=1
; RV32IA-NEXT: mv a2, s2
@@ -3626,10 +3624,9 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a0, s2, a4
; RV32I-NEXT: .LBB46_5: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: mv a2, a4
; RV32I-NEXT: mv a3, a5
-; RV32I-NEXT: bnez a0, .LBB46_1
+; RV32I-NEXT: beqz a0, .LBB46_1
; RV32I-NEXT: # %bb.6: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32I-NEXT: mv a2, s2
@@ -3681,10 +3678,9 @@ define signext i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind {
; RV32IA-NEXT: sltu a0, s2, a4
; RV32IA-NEXT: .LBB46_5: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: mv a2, a4
; RV32IA-NEXT: mv a3, a5
-; RV32IA-NEXT: bnez a0, .LBB46_1
+; RV32IA-NEXT: beqz a0, .LBB46_1
; RV32IA-NEXT: # %bb.6: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB46_2 Depth=1
; RV32IA-NEXT: mv a2, s2
diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
index f23d2590bf95ef..527fa6e1867852 100644
--- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
+++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
@@ -478,10 +478,10 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; RV32I-NEXT: sltu a0, a5, s1
; RV32I-NEXT: .LBB3_2: # %atomicrmw.start
; RV32I-NEXT: # in Loop: Header=BB3_3 Depth=1
-; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: addi a1, a4, 1
; RV32I-NEXT: seqz a2, a1
; RV32I-NEXT: add a3, a5, a2
+; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: and a2, a0, a1
; RV32I-NEXT: and a3, a0, a3
@@ -534,10 +534,10 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) {
; RV32IA-NEXT: sltu a0, a5, s1
; RV32IA-NEXT: .LBB3_2: # %atomicrmw.start
; RV32IA-NEXT: # in Loop: Header=BB3_3 Depth=1
-; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: addi a1, a4, 1
; RV32IA-NEXT: seqz a2, a1
; RV32IA-NEXT: add a3, a5, a2
+; RV32IA-NEXT: xori a0, a0, 1
; RV32IA-NEXT: addi a0, a0, -1
; RV32IA-NEXT: and a2, a0, a1
; RV32IA-NEXT: and a3, a0, a3
diff --git a/llvm/test/CodeGen/RISCV/condops.ll b/llvm/test/CodeGen/RISCV/condops.ll
index 19018a3e461b46..7e5a58368e7072 100644
--- a/llvm/test/CodeGen/RISCV/condops.ll
+++ b/llvm/test/CodeGen/RISCV/condops.ll
@@ -1264,13 +1264,11 @@ define i64 @setge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-NEXT: beq a1, a3, .LBB24_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a1, a3
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: beqz a0, .LBB24_3
+; RV32I-NEXT: bnez a0, .LBB24_3
; RV32I-NEXT: j .LBB24_4
; RV32I-NEXT: .LBB24_2:
; RV32I-NEXT: sltu a0, a0, a2
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: bnez a0, .LBB24_4
+; RV32I-NEXT: beqz a0, .LBB24_4
; RV32I-NEXT: .LBB24_3:
; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7
@@ -1410,13 +1408,11 @@ define i64 @setle(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-NEXT: beq a1, a3, .LBB26_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a3, a1
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: beqz a0, .LBB26_3
+; RV32I-NEXT: bnez a0, .LBB26_3
; RV32I-NEXT: j .LBB26_4
; RV32I-NEXT: .LBB26_2:
; RV32I-NEXT: sltu a0, a2, a0
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: bnez a0, .LBB26_4
+; RV32I-NEXT: beqz a0, .LBB26_4
; RV32I-NEXT: .LBB26_3:
; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7
@@ -1556,13 +1552,11 @@ define i64 @setuge(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-NEXT: beq a1, a3, .LBB28_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a1, a3
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: beqz a0, .LBB28_3
+; RV32I-NEXT: bnez a0, .LBB28_3
; RV32I-NEXT: j .LBB28_4
; RV32I-NEXT: .LBB28_2:
; RV32I-NEXT: sltu a0, a0, a2
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: bnez a0, .LBB28_4
+; RV32I-NEXT: beqz a0, .LBB28_4
; RV32I-NEXT: .LBB28_3:
; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7
@@ -1702,13 +1696,11 @@ define i64 @setule(i64 %a, i64 %b, i64 %rs1, i64 %rs2) {
; RV32I-NEXT: beq a1, a3, .LBB30_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a3, a1
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: beqz a0, .LBB30_3
+; RV32I-NEXT: bnez a0, .LBB30_3
; RV32I-NEXT: j .LBB30_4
; RV32I-NEXT: .LBB30_2:
; RV32I-NEXT: sltu a0, a2, a0
-; RV32I-NEXT: xori a0, a0, 1
-; RV32I-NEXT: bnez a0, .LBB30_4
+; RV32I-NEXT: beqz a0, .LBB30_4
; RV32I-NEXT: .LBB30_3:
; RV32I-NEXT: mv a4, a6
; RV32I-NEXT: mv a5, a7
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