[llvm] 12832c1 - [RISCV] Add isAllocatable=0 to VCSR register class.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-25T08:54:59-07:00
New Revision: 12832c1773f520563601c85bd1163fc3e734d3e6

URL: https://github.com/llvm/llvm-project/commit/12832c1773f520563601c85bd1163fc3e734d3e6
DIFF: https://github.com/llvm/llvm-project/commit/12832c1773f520563601c85bd1163fc3e734d3e6.diff

LOG: [RISCV] Add isAllocatable=0 to VCSR register class.

This avoids creating an unnecessary register pressure set.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D156196

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 0b17f54431efad..b23785cd230204 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -461,6 +461,7 @@ def VLENB  : RISCVReg<0, "vlenb">,
 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
                           (add VTYPE, VL, VLENB)> {
   let RegInfos = XLenRI;
+  let isAllocatable = 0;
 }