[PATCH] D156196: [RISCV] Add isAllocatable=0 to VCSR register class.

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156196/new/

https://reviews.llvm.org/D156196