[llvm] 395cd33 - AMDGPU: Remove trailing whitespace from documentation

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2023-07-25T07:54:11-04:00
New Revision: 395cd33ba850989209834a2e332d21b42168cfaf

URL: https://github.com/llvm/llvm-project/commit/395cd33ba850989209834a2e332d21b42168cfaf
DIFF: https://github.com/llvm/llvm-project/commit/395cd33ba850989209834a2e332d21b42168cfaf.diff

LOG: AMDGPU: Remove trailing whitespace from documentation

Added: 
    

Modified: 
    llvm/docs/AMDGPUUsage.rst

Removed: 
    


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diff  --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst
index d90c83f7e8e7dd..0a7ae20e9b1c8c 100644
--- a/llvm/docs/AMDGPUUsage.rst
+++ b/llvm/docs/AMDGPUUsage.rst
@@ -999,21 +999,21 @@ The AMDGPU backend implements the following LLVM IR intrinsics.
                                              marked with the :ref:`afn <fastmath_afn>` flag.
 
   llvm.amdgcn.wave.reduce.umin               Performs an arithmetic unsigned min reduction on the unsigned values
-                                             provided by each lane in the wavefront. 
+                                             provided by each lane in the wavefront.
                                              Intrinsic takes a hint for reduction strategy using second operand
                                              0: Target default preference,
                                              1: `Iterative strategy`, and
-                                             2: `DPP`. 
+                                             2: `DPP`.
                                              If target does not support the DPP operations (e.g. gfx6/7),
                                              reduction will be performed using default iterative strategy.
                                              Intrinsic is currently only implemented for i32.
 
-  llvm.amdgcn.wave.reduce.umax               Performs an arithmetic unsigned max reduction on the unsigned values 
+  llvm.amdgcn.wave.reduce.umax               Performs an arithmetic unsigned max reduction on the unsigned values
                                              provided by each lane in the wavefront.
                                              Intrinsic takes a hint for reduction strategy using second operand
                                              0: Target default preference,
                                              1: `Iterative strategy`, and
-                                             2: `DPP`. 
+                                             2: `DPP`.
                                              If target does not support the DPP operations (e.g. gfx6/7),
                                              reduction will be performed using default iterative strategy.
                                              Intrinsic is currently only implemented for i32.