[PATCH] D154488: [PowerPC] Define SchedModel for Power8

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/atomics-i128.ll:510
 ; PPC-PWR8-NEXT:    bl __atomic_compare_exchange
-; PPC-PWR8-NEXT:    cmplwi r3, 0
+; PPC-PWR8-NEXT:    mr r7, r3
 ; PPC-PWR8-NEXT:    lwz r6, 44(r1)
----------------
shchenz wrote:
> negative change, now we have more `mr` which is not free on pwr8.
The BB with negative result is quite simple:

```
SU(0):   %29:gprc = COPY $r3
SU(1):   %34:gprc = LWZ 12, %stack.0
SU(2):   %33:gprc = LWZ 8, %stack.0
SU(3):   %32:gprc = LWZ 4, %stack.0
SU(4):   %31:gprc = LWZ 0, %stack.0
SU(5):   %30:crrc = CMPLWI %29:gprc, 0
```

The old scheduling model puts `SU(5)` just after `SU(0)`, so that `%29:gprc` is assigned with `r3`. With the new scheduling model, the BB is unchanged after pre-isel scheduling.

I think it's more likely an issue of the scheduler exposed by new model and I'll further look at why regpressure is not respected here. But here I'm curious why the register allocator not assign `r3` to `%29`.


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  https://reviews.llvm.org/D154488/new/

https://reviews.llvm.org/D154488