[PATCH] D156140: [DAGCombiner] Minor improvements to foldAndOrOfSETCC. NFC

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG1f5a1b895292: [DAGCombiner] Minor improvements to foldAndOrOfSETCC. NFC (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156140/new/

https://reviews.llvm.org/D156140

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6054,10 +6054,6 @@
       TLI.isOperationLegal(ISD::SMAX, OpVT) &&
       TLI.isOperationLegal(ISD::UMIN, OpVT) &&
       TLI.isOperationLegal(ISD::SMIN, OpVT)) {
-    SDValue CommonValue;
-    SDValue Operand1;
-    SDValue Operand2;
-    ISD::CondCode CC = ISD::SETCC_INVALID;
     if (LHS->getOpcode() == ISD::SETCC && RHS->getOpcode() == ISD::SETCC &&
         LHS->hasOneUse() && RHS->hasOneUse() &&
         // The two comparisons should have either the same predicate or the
@@ -6065,6 +6061,8 @@
         (CCL == CCR || CCL == ISD::getSetCCSwappedOperands(CCR)) &&
         // The optimization does not work for `==` or `!=` .
         !ISD::isIntEqualitySetCC(CCL) && !ISD::isIntEqualitySetCC(CCR)) {
+      SDValue CommonValue, Operand1, Operand2;
+      ISD::CondCode CC = ISD::SETCC_INVALID;
       if (CCL == CCR) {
         if (LHS0 == RHS0) {
           CommonValue = LHS0;
@@ -6077,7 +6075,8 @@
           Operand2 = RHS0;
           CC = CCL;
         }
-      } else if (CCL == ISD::getSetCCSwappedOperands(CCR)) {
+      } else {
+        assert(CCL == ISD::getSetCCSwappedOperands(CCR) && "Unexpected CC");
         if (LHS0 == RHS1) {
           CommonValue = LHS0;
           Operand1 = LHS1;


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