[PATCH] D153721: [RISCV] Add support for XCVsimd extension in CV32E40P

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:224
+  let Inst{11-7} = rd;
+  let Opcode = opcode.Value;
+  let DecoderNamespace = "CoreVSIMD";
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This needs to be rebased. The `Opcode` field no longer exists. You should assign `Inst{6-0}` directly


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153721/new/

https://reviews.llvm.org/D153721