[PATCH] D153721: [RISCV] Add support for XCVsimd extension in CV32E40P

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/docs/RISCVUsage.rst:279
+
+``XCVsimd``
+  LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification.
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Put this above XSfcie?


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Comment at: llvm/docs/RISCVUsage.rst:280
+``XCVsimd``
+  LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by Core-V.  All instructions are prefixed with `cv.` as described in the specification.
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Is it CORE-V or Core-V? Previous extensions said "by OpenHW Group" rather than "by Core-V".


Repository:
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  https://reviews.llvm.org/D153721/new/

https://reviews.llvm.org/D153721