[PATCH] D153721: [RISCV] Add support for XCVsimd extension in CV32E40P
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 24 13:37:30 PDT 2023
craig.topper added inline comments.
================
Comment at: llvm/docs/RISCVUsage.rst:279
+
+``XCVsimd``
+ LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by Core-V. All instructions are prefixed with `cv.` as described in the specification.
----------------
Put this above XSfcie?
================
Comment at: llvm/docs/RISCVUsage.rst:280
+``XCVsimd``
+ LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/cv32e40p_v1.3.2/docs/source/instruction_set_extensions.rst>`_ by Core-V. All instructions are prefixed with `cv.` as described in the specification.
----------------
Is it CORE-V or Core-V? Previous extensions said "by OpenHW Group" rather than "by Core-V".
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D153721/new/
https://reviews.llvm.org/D153721
More information about the llvm-commits
mailing list