[llvm] 5e32f1d - [NVPTX] Expand select_cc on bfloat16 type
Benjamin Kramer via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 24 08:10:32 PDT 2023
Author: Yuanqiang Liu
Date: 2023-07-24T17:01:31+02:00
New Revision: 5e32f1da063f8982946a1156dc4ee75e867e6ec8
URL: https://github.com/llvm/llvm-project/commit/5e32f1da063f8982946a1156dc4ee75e867e6ec8
DIFF: https://github.com/llvm/llvm-project/commit/5e32f1da063f8982946a1156dc4ee75e867e6ec8.diff
LOG: [NVPTX] Expand select_cc on bfloat16 type
Expand select_cc on bfloat16 and bfloat16v2 type.
Differential Revision: https://reviews.llvm.org/D156085
Added:
Modified:
llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
llvm/test/CodeGen/NVPTX/bf16-instructions.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
index fa050bcdc34121..7823e12d627066 100644
--- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -460,8 +460,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote);
setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand);
// Operations not directly supported by NVPTX.
- for (MVT VT : {MVT::f16, MVT::v2f16, MVT::f32, MVT::f64, MVT::i1, MVT::i8,
- MVT::i16, MVT::i32, MVT::i64}) {
+ for (MVT VT : {MVT::bf16, MVT::f16, MVT::v2bf16, MVT::v2f16, MVT::f32,
+ MVT::f64, MVT::i1, MVT::i8, MVT::i16, MVT::i32, MVT::i64}) {
setOperationAction(ISD::SELECT_CC, VT, Expand);
setOperationAction(ISD::BR_CC, VT, Expand);
}
diff --git a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
index 3373cf1401aae4..a2c995f61cb14d 100644
--- a/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16-instructions.ll
@@ -192,3 +192,18 @@ define bfloat @test_fadd_imm_1(bfloat %a) #0 {
%r = fadd bfloat %a, 1.0
ret bfloat %r
}
+
+; CHECK-LABEL: test_select_cc_bf16_f64(
+; CHECK-DAG: ld.param.f64 [[A:%fd[0-9]+]], [test_select_cc_bf16_f64_param_0];
+; CHECK-DAG: ld.param.f64 [[B:%fd[0-9]+]], [test_select_cc_bf16_f64_param_1];
+; CHECK: setp.lt.f64 [[P:%p[0-9]+]], [[A]], [[B]];
+; CHECK-DAG: ld.param.b16 [[C:%rs[0-9]+]], [test_select_cc_bf16_f64_param_2];
+; CHECK-DAG: ld.param.b16 [[D:%rs[0-9]+]], [test_select_cc_bf16_f64_param_3];
+; CHECK: selp.b16 [[R:%rs[0-9]+]], [[C]], [[D]], [[P]];
+; CHECK-NEXT: st.param.b16 [func_retval0+0], [[R]];
+; CHECK-NEXT: ret;
+define bfloat @test_select_cc_bf16_f64(double %a, double %b, bfloat %c, bfloat %d) #0 {
+ %cc = fcmp olt double %a, %b
+ %r = select i1 %cc, bfloat %c, bfloat %d
+ ret bfloat %r
+}
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