[PATCH] D156094: [AArch64] Ignore instructions not supported by CPU in AArch64SVESchedPseudoTest

[Sander de Smalen via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG57329ca94630: [AArch64] Ignore instructions not supported by CPU in AArch64SVESchedPseudoTest (authored by sdesmalen).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D156094/new/

https://reviews.llvm.org/D156094

Files:
  llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp


Index: llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp
===================================================================
--- llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp
+++ llvm/unittests/Target/AArch64/AArch64SVESchedPseudoTest.cpp
@@ -4,6 +4,7 @@
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
@@ -33,6 +34,22 @@
   return std::make_unique<AArch64InstrInfo>(ST);
 }
 
+#define GET_COMPUTE_FEATURES
+#include "AArch64GenInstrInfo.inc"
+
+/// Returns true if the instruction is enabled under a feature that the
+/// CPU supports.
+static bool isInstructionSupportedByCPU(unsigned Opcode,
+                                        FeatureBitset Features) {
+  FeatureBitset AvailableFeatures =
+      llvm::AArch64_MC::computeAvailableFeatures(Features);
+  FeatureBitset RequiredFeatures =
+      llvm::AArch64_MC::computeRequiredFeatures(Opcode);
+  FeatureBitset MissingFeatures =
+      (AvailableFeatures & RequiredFeatures) ^ RequiredFeatures;
+  return MissingFeatures.none();
+}
+
 void runSVEPseudoTestForCPU(const std::string &CPU) {
 
   std::unique_ptr<LLVMTargetMachine> TM = createTargetMachine(CPU);
@@ -51,6 +68,13 @@
     if (OrigInstr == -1)
       continue;
 
+    // Ignore any pseudos/instructions which may not be part of the scheduler
+    // model for the CPU we're testing. This avoids this test from failing when
+    // new instructions are added that are not yet covered by the scheduler
+    // model.
+    if (!isInstructionSupportedByCPU(OrigInstr, STI->getFeatureBits()))
+      continue;
+
     const MCInstrDesc &Desc = II->get(i);
     unsigned SCClass = Desc.getSchedClass();
     const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCClass);


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