[llvm] 1e86b63 - [X86] fpclamptosat.ll - add nounwind to get rid of cfi noise
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 24 07:11:40 PDT 2023
Author: Simon Pilgrim
Date: 2023-07-24T15:11:26+01:00
New Revision: 1e86b63eb30fdb266100087d8b1352046b29723a
URL: https://github.com/llvm/llvm-project/commit/1e86b63eb30fdb266100087d8b1352046b29723a
DIFF: https://github.com/llvm/llvm-project/commit/1e86b63eb30fdb266100087d8b1352046b29723a.diff
LOG: [X86] fpclamptosat.ll - add nounwind to get rid of cfi noise
Helps cleanup D150372
Added:
Modified:
llvm/test/CodeGen/X86/fpclamptosat.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/fpclamptosat.ll b/llvm/test/CodeGen/X86/fpclamptosat.ll
index 87e9a587d31ea7..a194f669fd5b91 100644
--- a/llvm/test/CodeGen/X86/fpclamptosat.ll
+++ b/llvm/test/CodeGen/X86/fpclamptosat.ll
@@ -3,7 +3,7 @@
; i32 saturate
-define i32 @stest_f64i32(double %x) {
+define i32 @stest_f64i32(double %x) nounwind {
; CHECK-LABEL: stest_f64i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
@@ -23,7 +23,7 @@ entry:
ret i32 %conv6
}
-define i32 @utest_f64i32(double %x) {
+define i32 @utest_f64i32(double %x) nounwind {
; CHECK-LABEL: utest_f64i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rax
@@ -46,7 +46,7 @@ entry:
ret i32 %conv6
}
-define i32 @ustest_f64i32(double %x) {
+define i32 @ustest_f64i32(double %x) nounwind {
; CHECK-LABEL: ustest_f64i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rcx
@@ -68,7 +68,7 @@ entry:
ret i32 %conv6
}
-define i32 @stest_f32i32(float %x) {
+define i32 @stest_f32i32(float %x) nounwind {
; CHECK-LABEL: stest_f32i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %eax
@@ -89,7 +89,7 @@ entry:
ret i32 %conv6
}
-define i32 @utest_f32i32(float %x) {
+define i32 @utest_f32i32(float %x) nounwind {
; CHECK-LABEL: utest_f32i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %rax
@@ -112,7 +112,7 @@ entry:
ret i32 %conv6
}
-define i32 @ustest_f32i32(float %x) {
+define i32 @ustest_f32i32(float %x) nounwind {
; CHECK-LABEL: ustest_f32i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %rcx
@@ -134,11 +134,10 @@ entry:
ret i32 %conv6
}
-define i32 @stest_f16i32(half %x) {
+define i32 @stest_f16i32(half %x) nounwind {
; CHECK-LABEL: stest_f16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -151,7 +150,6 @@ define i32 @stest_f16i32(half %x) {
; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovnpl %edx, %eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i64
@@ -163,11 +161,10 @@ entry:
ret i32 %conv6
}
-define i32 @utesth_f16i32(half %x) {
+define i32 @utesth_f16i32(half %x) nounwind {
; CHECK-LABEL: utesth_f16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movq %rax, %rcx
@@ -181,7 +178,6 @@ define i32 @utesth_f16i32(half %x) {
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cmovbl %edx, %eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui half %x to i64
@@ -191,11 +187,10 @@ entry:
ret i32 %conv6
}
-define i32 @ustest_f16i32(half %x) {
+define i32 @ustest_f16i32(half %x) nounwind {
; CHECK-LABEL: ustest_f16i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %rcx
; CHECK-NEXT: movl $4294967295, %eax # imm = 0xFFFFFFFF
@@ -206,7 +201,6 @@ define i32 @ustest_f16i32(half %x) {
; CHECK-NEXT: cmovlel %ecx, %eax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i64
@@ -220,7 +214,7 @@ entry:
; i16 saturate
-define i16 @stest_f64i16(double %x) {
+define i16 @stest_f64i16(double %x) nounwind {
; CHECK-LABEL: stest_f64i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
@@ -240,7 +234,7 @@ entry:
ret i16 %conv6
}
-define i16 @utest_f64i16(double %x) {
+define i16 @utest_f64i16(double %x) nounwind {
; CHECK-LABEL: utest_f64i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rcx
@@ -257,7 +251,7 @@ entry:
ret i16 %conv6
}
-define i16 @ustest_f64i16(double %x) {
+define i16 @ustest_f64i16(double %x) nounwind {
; CHECK-LABEL: ustest_f64i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %eax
@@ -279,7 +273,7 @@ entry:
ret i16 %conv6
}
-define i16 @stest_f32i16(float %x) {
+define i16 @stest_f32i16(float %x) nounwind {
; CHECK-LABEL: stest_f32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -299,7 +293,7 @@ entry:
ret i16 %conv6
}
-define i16 @utest_f32i16(float %x) {
+define i16 @utest_f32i16(float %x) nounwind {
; CHECK-LABEL: utest_f32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %rcx
@@ -316,7 +310,7 @@ entry:
ret i16 %conv6
}
-define i16 @ustest_f32i16(float %x) {
+define i16 @ustest_f32i16(float %x) nounwind {
; CHECK-LABEL: ustest_f32i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %eax
@@ -338,11 +332,10 @@ entry:
ret i16 %conv6
}
-define i16 @stest_f16i16(half %x) {
+define i16 @stest_f16i16(half %x) nounwind {
; CHECK-LABEL: stest_f16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -356,7 +349,6 @@ define i16 @stest_f16i16(half %x) {
; CHECK-NEXT: cmovnpl %edx, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i32
@@ -368,11 +360,10 @@ entry:
ret i16 %conv6
}
-define i16 @utesth_f16i16(half %x) {
+define i16 @utesth_f16i16(half %x) nounwind {
; CHECK-LABEL: utesth_f16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %rcx
; CHECK-NEXT: cmpl $65535, %ecx # imm = 0xFFFF
@@ -380,7 +371,6 @@ define i16 @utesth_f16i16(half %x) {
; CHECK-NEXT: cmovbl %ecx, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui half %x to i32
@@ -390,11 +380,10 @@ entry:
ret i16 %conv6
}
-define i16 @ustest_f16i16(half %x) {
+define i16 @ustest_f16i16(half %x) nounwind {
; CHECK-LABEL: ustest_f16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -405,7 +394,6 @@ define i16 @ustest_f16i16(half %x) {
; CHECK-NEXT: cmovgl %ecx, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i32
@@ -420,11 +408,10 @@ entry:
; i64 saturate
; FIXME: Failure to recognise the i128 is in i64 bounds.
-define i64 @stest_f64i64(double %x) {
+define i64 @stest_f64i64(double %x) nounwind {
; CHECK-LABEL: stest_f64i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixdfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
@@ -439,7 +426,6 @@ define i64 @stest_f64i64(double %x) {
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: cmovgeq %rdx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi double %x to i128
@@ -451,17 +437,15 @@ entry:
ret i64 %conv6
}
-define i64 @utest_f64i64(double %x) {
+define i64 @utest_f64i64(double %x) nounwind {
; CHECK-LABEL: utest_f64i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixunsdfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui double %x to i128
@@ -471,11 +455,10 @@ entry:
ret i64 %conv6
}
-define i64 @ustest_f64i64(double %x) {
+define i64 @ustest_f64i64(double %x) nounwind {
; CHECK-LABEL: ustest_f64i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixdfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
@@ -488,7 +471,6 @@ define i64 @ustest_f64i64(double %x) {
; CHECK-NEXT: sbbq %rsi, %rdx
; CHECK-NEXT: cmovgeq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi double %x to i128
@@ -501,11 +483,10 @@ entry:
}
; FIXME: Failure to recognise the i128 is in i64 bounds.
-define i64 @stest_f32i64(float %x) {
+define i64 @stest_f32i64(float %x) nounwind {
; CHECK-LABEL: stest_f32i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixsfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
@@ -520,7 +501,6 @@ define i64 @stest_f32i64(float %x) {
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: cmovgeq %rdx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi float %x to i128
@@ -532,17 +512,15 @@ entry:
ret i64 %conv6
}
-define i64 @utest_f32i64(float %x) {
+define i64 @utest_f32i64(float %x) nounwind {
; CHECK-LABEL: utest_f32i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixunssfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui float %x to i128
@@ -552,11 +530,10 @@ entry:
ret i64 %conv6
}
-define i64 @ustest_f32i64(float %x) {
+define i64 @ustest_f32i64(float %x) nounwind {
; CHECK-LABEL: ustest_f32i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixsfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
@@ -569,7 +546,6 @@ define i64 @ustest_f32i64(float %x) {
; CHECK-NEXT: sbbq %rsi, %rdx
; CHECK-NEXT: cmovgeq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi float %x to i128
@@ -582,11 +558,10 @@ entry:
}
; FIXME: Failure to recognise the i128 is in i64 bounds.
-define i64 @stest_f16i64(half %x) {
+define i64 @stest_f16i64(half %x) nounwind {
; CHECK-LABEL: stest_f16i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixhfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: movabsq $9223372036854775807, %rsi # imm = 0x7FFFFFFFFFFFFFFF
@@ -601,7 +576,6 @@ define i64 @stest_f16i64(half %x) {
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: cmovgeq %rdx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i128
@@ -613,17 +587,15 @@ entry:
ret i64 %conv6
}
-define i64 @utesth_f16i64(half %x) {
+define i64 @utesth_f16i64(half %x) nounwind {
; CHECK-LABEL: utesth_f16i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixunshfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui half %x to i128
@@ -633,11 +605,10 @@ entry:
ret i64 %conv6
}
-define i64 @ustest_f16i64(half %x) {
+define i64 @ustest_f16i64(half %x) nounwind {
; CHECK-LABEL: ustest_f16i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixhfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
@@ -650,7 +621,6 @@ define i64 @ustest_f16i64(half %x) {
; CHECK-NEXT: sbbq %rsi, %rdx
; CHECK-NEXT: cmovgeq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i128
@@ -667,7 +637,7 @@ entry:
; i32 saturate
-define i32 @stest_f64i32_mm(double %x) {
+define i32 @stest_f64i32_mm(double %x) nounwind {
; CHECK-LABEL: stest_f64i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
@@ -685,7 +655,7 @@ entry:
ret i32 %conv6
}
-define i32 @utest_f64i32_mm(double %x) {
+define i32 @utest_f64i32_mm(double %x) nounwind {
; CHECK-LABEL: utest_f64i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rcx
@@ -707,7 +677,7 @@ entry:
ret i32 %conv6
}
-define i32 @ustest_f64i32_mm(double %x) {
+define i32 @ustest_f64i32_mm(double %x) nounwind {
; CHECK-LABEL: ustest_f64i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rax
@@ -727,7 +697,7 @@ entry:
ret i32 %conv6
}
-define i32 @stest_f32i32_mm(float %x) {
+define i32 @stest_f32i32_mm(float %x) nounwind {
; CHECK-LABEL: stest_f32i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %eax
@@ -746,7 +716,7 @@ entry:
ret i32 %conv6
}
-define i32 @utest_f32i32_mm(float %x) {
+define i32 @utest_f32i32_mm(float %x) nounwind {
; CHECK-LABEL: utest_f32i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %rcx
@@ -768,7 +738,7 @@ entry:
ret i32 %conv6
}
-define i32 @ustest_f32i32_mm(float %x) {
+define i32 @ustest_f32i32_mm(float %x) nounwind {
; CHECK-LABEL: ustest_f32i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %rax
@@ -788,11 +758,10 @@ entry:
ret i32 %conv6
}
-define i32 @stest_f16i32_mm(half %x) {
+define i32 @stest_f16i32_mm(half %x) nounwind {
; CHECK-LABEL: stest_f16i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -805,7 +774,6 @@ define i32 @stest_f16i32_mm(half %x) {
; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovnpl %edx, %eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i64
@@ -815,11 +783,10 @@ entry:
ret i32 %conv6
}
-define i32 @utesth_f16i32_mm(half %x) {
+define i32 @utesth_f16i32_mm(half %x) nounwind {
; CHECK-LABEL: utesth_f16i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %rcx
; CHECK-NEXT: movq %rcx, %rdx
@@ -833,7 +800,6 @@ define i32 @utesth_f16i32_mm(half %x) {
; CHECK-NEXT: cmovaeq %rcx, %rax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui half %x to i64
@@ -842,11 +808,10 @@ entry:
ret i32 %conv6
}
-define i32 @ustest_f16i32_mm(half %x) {
+define i32 @ustest_f16i32_mm(half %x) nounwind {
; CHECK-LABEL: ustest_f16i32_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF
@@ -857,7 +822,6 @@ define i32 @ustest_f16i32_mm(half %x) {
; CHECK-NEXT: cmovgq %rcx, %rax
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i64
@@ -869,7 +833,7 @@ entry:
; i16 saturate
-define i16 @stest_f64i16_mm(double %x) {
+define i16 @stest_f64i16_mm(double %x) nounwind {
; CHECK-LABEL: stest_f64i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
@@ -887,7 +851,7 @@ entry:
ret i16 %conv6
}
-define i16 @utest_f64i16_mm(double %x) {
+define i16 @utest_f64i16_mm(double %x) nounwind {
; CHECK-LABEL: utest_f64i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rcx
@@ -903,7 +867,7 @@ entry:
ret i16 %conv6
}
-define i16 @ustest_f64i16_mm(double %x) {
+define i16 @ustest_f64i16_mm(double %x) nounwind {
; CHECK-LABEL: ustest_f64i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %eax
@@ -923,7 +887,7 @@ entry:
ret i16 %conv6
}
-define i16 @stest_f32i16_mm(float %x) {
+define i16 @stest_f32i16_mm(float %x) nounwind {
; CHECK-LABEL: stest_f32i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
@@ -941,7 +905,7 @@ entry:
ret i16 %conv6
}
-define i16 @utest_f32i16_mm(float %x) {
+define i16 @utest_f32i16_mm(float %x) nounwind {
; CHECK-LABEL: utest_f32i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %rcx
@@ -957,7 +921,7 @@ entry:
ret i16 %conv6
}
-define i16 @ustest_f32i16_mm(float %x) {
+define i16 @ustest_f32i16_mm(float %x) nounwind {
; CHECK-LABEL: ustest_f32i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %eax
@@ -977,11 +941,10 @@ entry:
ret i16 %conv6
}
-define i16 @stest_f16i16_mm(half %x) {
+define i16 @stest_f16i16_mm(half %x) nounwind {
; CHECK-LABEL: stest_f16i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -995,7 +958,6 @@ define i16 @stest_f16i16_mm(half %x) {
; CHECK-NEXT: cmovnpl %edx, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i32
@@ -1005,11 +967,10 @@ entry:
ret i16 %conv6
}
-define i16 @utesth_f16i16_mm(half %x) {
+define i16 @utesth_f16i16_mm(half %x) nounwind {
; CHECK-LABEL: utesth_f16i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %rcx
; CHECK-NEXT: cmpl $65535, %ecx # imm = 0xFFFF
@@ -1017,7 +978,6 @@ define i16 @utesth_f16i16_mm(half %x) {
; CHECK-NEXT: cmovbl %ecx, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui half %x to i32
@@ -1026,11 +986,10 @@ entry:
ret i16 %conv6
}
-define i16 @ustest_f16i16_mm(half %x) {
+define i16 @ustest_f16i16_mm(half %x) nounwind {
; CHECK-LABEL: ustest_f16i16_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %eax
; CHECK-NEXT: cmpl $65535, %eax # imm = 0xFFFF
@@ -1041,7 +1000,6 @@ define i16 @ustest_f16i16_mm(half %x) {
; CHECK-NEXT: cmovgl %ecx, %eax
; CHECK-NEXT: # kill: def $ax killed $ax killed $eax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i32
@@ -1053,7 +1011,7 @@ entry:
; i64 saturate
-define i64 @stest_f64i64_mm(double %x) {
+define i64 @stest_f64i64_mm(double %x) nounwind {
; CHECK-LABEL: stest_f64i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttsd2si %xmm0, %rax
@@ -1072,17 +1030,15 @@ entry:
ret i64 %conv6
}
-define i64 @utest_f64i64_mm(double %x) {
+define i64 @utest_f64i64_mm(double %x) nounwind {
; CHECK-LABEL: utest_f64i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixunsdfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui double %x to i128
@@ -1091,11 +1047,10 @@ entry:
ret i64 %conv6
}
-define i64 @ustest_f64i64_mm(double %x) {
+define i64 @ustest_f64i64_mm(double %x) nounwind {
; CHECK-LABEL: ustest_f64i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixdfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
@@ -1105,7 +1060,6 @@ define i64 @ustest_f64i64_mm(double %x) {
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: cmovsq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi double %x to i128
@@ -1115,7 +1069,7 @@ entry:
ret i64 %conv6
}
-define i64 @stest_f32i64_mm(float %x) {
+define i64 @stest_f32i64_mm(float %x) nounwind {
; CHECK-LABEL: stest_f32i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cvttss2si %xmm0, %rax
@@ -1134,17 +1088,15 @@ entry:
ret i64 %conv6
}
-define i64 @utest_f32i64_mm(float %x) {
+define i64 @utest_f32i64_mm(float %x) nounwind {
; CHECK-LABEL: utest_f32i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixunssfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui float %x to i128
@@ -1153,11 +1105,10 @@ entry:
ret i64 %conv6
}
-define i64 @ustest_f32i64_mm(float %x) {
+define i64 @ustest_f32i64_mm(float %x) nounwind {
; CHECK-LABEL: ustest_f32i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixsfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
@@ -1167,7 +1118,6 @@ define i64 @ustest_f32i64_mm(float %x) {
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: cmovsq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi float %x to i128
@@ -1177,11 +1127,10 @@ entry:
ret i64 %conv6
}
-define i64 @stest_f16i64_mm(half %x) {
+define i64 @stest_f16i64_mm(half %x) nounwind {
; CHECK-LABEL: stest_f16i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __extendhfsf2 at PLT
; CHECK-NEXT: cvttss2si %xmm0, %rax
; CHECK-NEXT: ucomiss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0
@@ -1194,7 +1143,6 @@ define i64 @stest_f16i64_mm(half %x) {
; CHECK-NEXT: ucomiss %xmm0, %xmm0
; CHECK-NEXT: cmovnpq %rdx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i128
@@ -1204,17 +1152,15 @@ entry:
ret i64 %conv6
}
-define i64 @utesth_f16i64_mm(half %x) {
+define i64 @utesth_f16i64_mm(half %x) nounwind {
; CHECK-LABEL: utesth_f16i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixunshfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
; CHECK-NEXT: cmovneq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptoui half %x to i128
@@ -1223,11 +1169,10 @@ entry:
ret i64 %conv6
}
-define i64 @ustest_f16i64_mm(half %x) {
+define i64 @ustest_f16i64_mm(half %x) nounwind {
; CHECK-LABEL: ustest_f16i64_mm:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
-; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: callq __fixhfti at PLT
; CHECK-NEXT: xorl %ecx, %ecx
; CHECK-NEXT: testq %rdx, %rdx
@@ -1237,7 +1182,6 @@ define i64 @ustest_f16i64_mm(half %x) {
; CHECK-NEXT: testq %rsi, %rsi
; CHECK-NEXT: cmovsq %rcx, %rax
; CHECK-NEXT: popq %rcx
-; CHECK-NEXT: .cfi_def_cfa_offset 8
; CHECK-NEXT: retq
entry:
%conv = fptosi half %x to i128
More information about the llvm-commits
mailing list