[PATCH] D155565: [AArch64] SelectionDAG Funnel Shift Lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

I looked into the BE i20 case but considering how narrow in scope it is, I think this will be OK.

LGTM, with a couple of extra suggestions.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:5809
+  SDValue Shifts = Op.getOperand(2);
+  // Check then cast if the number of shifts is a constant
+  if (auto *ShiftNo = dyn_cast<ConstantSDNode>(Shifts)) {
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I'm not sure what this comment means. Is it just explaining that the funnel shifts with constant shift amounts are legal or converted to FSHR?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:5815
+    if (Op.getOpcode() == ISD::FSHL) {
+      long unsigned int NewShiftNo =
+          VT.getFixedSizeInBits() - ShiftNo->getZExtValue();
----------------
`unsigned` on its own is commonly used in LLVM as a type.


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https://reviews.llvm.org/D155565