[llvm] cea980f - [RISCV] Add tests for (and (add x, c1), (lshr y, c2))

[Weining Lu via llvm-commits]

Author: WANG Rui
Date: 2023-07-24T16:52:02+08:00
New Revision: cea980f380e1966892cf8a45064e46c757803bd1

URL: https://github.com/llvm/llvm-project/commit/cea980f380e1966892cf8a45064e46c757803bd1
DIFF: https://github.com/llvm/llvm-project/commit/cea980f380e1966892cf8a45064e46c757803bd1.diff

LOG: [RISCV] Add tests for (and (add x, c1), (lshr y, c2))

Add tests for (and (add x, c1), (lshr y, c2)).

Signed-off-by: WANG Rui <wangrui at loongson.cn>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D154808

Added: 
    llvm/test/CodeGen/RISCV/and-add-lsr.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/and-add-lsr.ll b/llvm/test/CodeGen/RISCV/and-add-lsr.ll
new file mode 100644
index 00000000000000..e25072775e5ac0
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/and-add-lsr.ll
@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV64I
+
+define i32 @and_add_lsr(i32 %x, i32 %y) {
+; RV32I-LABEL: and_add_lsr:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a2, 1
+; RV32I-NEXT:    addi a2, a2, -1
+; RV32I-NEXT:    add a0, a0, a2
+; RV32I-NEXT:    srli a1, a1, 20
+; RV32I-NEXT:    and a0, a1, a0
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and_add_lsr:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a2, 1
+; RV64I-NEXT:    addiw a2, a2, -1
+; RV64I-NEXT:    addw a0, a0, a2
+; RV64I-NEXT:    srliw a1, a1, 20
+; RV64I-NEXT:    and a0, a1, a0
+; RV64I-NEXT:    ret
+  %1 = add i32 %x, 4095
+  %2 = lshr i32 %y, 20
+  %r = and i32 %2, %1
+  ret i32 %r
+}