[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits (WIP)

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll:4710
-; GFX6-NEXT:    v_or_b32_e32 v2, v3, v2
-; GFX6-NEXT:    v_or_b32_e32 v0, v2, v0
-; GFX6-NEXT:    buffer_store_dword v0, off, s[0:3], 0
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I haven't managed to spot where the 64-bit shift that got removed is, but getting rid of them is really good


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155472/new/

https://reviews.llvm.org/D155472