[llvm] 6edc9a7 - [AArch64][GISel] Additional FPExt vector lowering
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 23 08:58:18 PDT 2023
Author: David Green
Date: 2023-07-23T16:58:13+01:00
New Revision: 6edc9a766213eed783e0b6dc5e2539ad925398f9
URL: https://github.com/llvm/llvm-project/commit/6edc9a766213eed783e0b6dc5e2539ad925398f9
DIFF: https://github.com/llvm/llvm-project/commit/6edc9a766213eed783e0b6dc5e2539ad925398f9.diff
LOG: [AArch64][GISel] Additional FPExt vector lowering
Similar to D155311, this adds lowering for more vector cases for FPExt
Differential Revision: https://reviews.llvm.org/D155601
Added:
llvm/test/CodeGen/AArch64/fpext.ll
Modified:
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index af5ff9ec943d58..f0da0d88140f2d 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -4950,7 +4950,8 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
Observer.changedInstr(MI);
return Legalized;
}
- case TargetOpcode::G_FPTRUNC: {
+ case TargetOpcode::G_FPTRUNC:
+ case TargetOpcode::G_FPEXT: {
if (TypeIdx != 0)
return UnableToLegalize;
Observer.changingInstr(MI);
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 67d47f08bce6b5..bb2fd35c9b4bae 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -541,7 +541,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_FPEXT)
.legalFor(
{{s32, s16}, {s64, s16}, {s64, s32}, {v4s32, v4s16}, {v2s64, v2s32}})
- .clampMaxNumElements(0, s64, 2);
+ .clampNumElements(0, v4s32, v4s32)
+ .clampNumElements(0, v2s64, v2s64)
+ .scalarize(0);
// Conversions
getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
diff --git a/llvm/test/CodeGen/AArch64/fpext.ll b/llvm/test/CodeGen/AArch64/fpext.ll
new file mode 100644
index 00000000000000..1b5a00885b29fe
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fpext.ll
@@ -0,0 +1,234 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel=0 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel=1 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+define double @fpext_f32_f64(float %a) {
+; CHECK-LABEL: fpext_f32_f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt d0, s0
+; CHECK-NEXT: ret
+entry:
+ %c = fpext float %a to double
+ ret double %c
+}
+
+define double @fpext_f16_f64(half %a) {
+; CHECK-LABEL: fpext_f16_f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt d0, h0
+; CHECK-NEXT: ret
+entry:
+ %c = fpext half %a to double
+ ret double %c
+}
+
+define float @fpext_f16_f32(half %a) {
+; CHECK-LABEL: fpext_f16_f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvt s0, h0
+; CHECK-NEXT: ret
+entry:
+ %c = fpext half %a to float
+ ret float %c
+}
+
+define <2 x double> @fpext_v2f32_v2f64(<2 x float> %a) {
+; CHECK-LABEL: fpext_v2f32_v2f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-NEXT: ret
+entry:
+ %c = fpext <2 x float> %a to <2 x double>
+ ret <2 x double> %c
+}
+
+define <3 x double> @fpext_v3f32_v3f64(<3 x float> %a) {
+; CHECK-SD-LABEL: fpext_v3f32_v3f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v3.2d, v0.2s
+; CHECK-SD-NEXT: fcvtl2 v2.2d, v0.4s
+; CHECK-SD-NEXT: // kill: def $d2 killed $d2 killed $q2
+; CHECK-SD-NEXT: fmov d0, d3
+; CHECK-SD-NEXT: ext v1.16b, v3.16b, v3.16b, #8
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v3f32_v3f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov s1, v0.s[2]
+; CHECK-GI-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-GI-NEXT: fcvt d2, s1
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+entry:
+ %c = fpext <3 x float> %a to <3 x double>
+ ret <3 x double> %c
+}
+
+define <4 x double> @fpext_v4f32_v4f64(<4 x float> %a) {
+; CHECK-SD-LABEL: fpext_v4f32_v4f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl2 v1.2d, v0.4s
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v4f32_v4f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl v1.2d, v1.2s
+; CHECK-GI-NEXT: ret
+entry:
+ %c = fpext <4 x float> %a to <4 x double>
+ ret <4 x double> %c
+}
+
+define <2 x double> @fpext_v2f16_v2f64(<2 x half> %a) {
+; CHECK-SD-LABEL: fpext_v2f16_v2f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NEXT: fcvt d0, h0
+; CHECK-SD-NEXT: fcvt d1, h1
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v2f16_v2f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NEXT: fcvt d0, h0
+; CHECK-GI-NEXT: fcvt d1, h1
+; CHECK-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %c = fpext <2 x half> %a to <2 x double>
+ ret <2 x double> %c
+}
+
+define <3 x double> @fpext_v3f16_v3f64(<3 x half> %a) {
+; CHECK-LABEL: fpext_v3f16_v3f64:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov h1, v0.h[1]
+; CHECK-NEXT: mov h2, v0.h[2]
+; CHECK-NEXT: fcvt d0, h0
+; CHECK-NEXT: fcvt d1, h1
+; CHECK-NEXT: fcvt d2, h2
+; CHECK-NEXT: ret
+entry:
+ %c = fpext <3 x half> %a to <3 x double>
+ ret <3 x double> %c
+}
+
+define <4 x double> @fpext_v4f16_v4f64(<4 x half> %a) {
+; CHECK-SD-LABEL: fpext_v4f16_v4f64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: mov h1, v0.h[1]
+; CHECK-SD-NEXT: mov h2, v0.h[3]
+; CHECK-SD-NEXT: mov h3, v0.h[2]
+; CHECK-SD-NEXT: fcvt d0, h0
+; CHECK-SD-NEXT: fcvt d4, h1
+; CHECK-SD-NEXT: fcvt d2, h2
+; CHECK-SD-NEXT: fcvt d1, h3
+; CHECK-SD-NEXT: mov v0.d[1], v4.d[0]
+; CHECK-SD-NEXT: mov v1.d[1], v2.d[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v4f16_v4f64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: mov h2, v0.h[1]
+; CHECK-GI-NEXT: fcvt d0, h0
+; CHECK-GI-NEXT: mov h3, v1.h[1]
+; CHECK-GI-NEXT: fcvt d2, h2
+; CHECK-GI-NEXT: fcvt d1, h1
+; CHECK-GI-NEXT: fcvt d3, h3
+; CHECK-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-GI-NEXT: mov v1.d[1], v3.d[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %c = fpext <4 x half> %a to <4 x double>
+ ret <4 x double> %c
+}
+
+define <2 x float> @fpext_v2f16_v2f32(<2 x half> %a) {
+; CHECK-SD-LABEL: fpext_v2f16_v2f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v2f16_v2f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fmov x8, d0
+; CHECK-GI-NEXT: fmov s0, w8
+; CHECK-GI-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NEXT: mov v0.h[2], v0.h[0]
+; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+entry:
+ %c = fpext <2 x half> %a to <2 x float>
+ ret <2 x float> %c
+}
+
+define <3 x float> @fpext_v3f16_v3f32(<3 x half> %a) {
+; CHECK-SD-LABEL: fpext_v3f16_v3f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v3f16_v3f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov h1, v0.h[1]
+; CHECK-GI-NEXT: mov h2, v0.h[2]
+; CHECK-GI-NEXT: mov v0.h[1], v1.h[0]
+; CHECK-GI-NEXT: mov v0.h[2], v2.h[0]
+; CHECK-GI-NEXT: mov v0.h[3], v0.h[0]
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: mov s2, v0.s[2]
+; CHECK-GI-NEXT: mov v0.s[1], v1.s[0]
+; CHECK-GI-NEXT: mov v0.s[2], v2.s[0]
+; CHECK-GI-NEXT: mov v0.s[3], v0.s[0]
+; CHECK-GI-NEXT: ret
+entry:
+ %c = fpext <3 x half> %a to <3 x float>
+ ret <3 x float> %c
+}
+
+define <4 x float> @fpext_v4f16_v4f32(<4 x half> %a) {
+; CHECK-LABEL: fpext_v4f16_v4f32:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-NEXT: ret
+entry:
+ %c = fpext <4 x half> %a to <4 x float>
+ ret <4 x float> %c
+}
+
+define <8 x float> @fpext_v8f16_v8f32(<8 x half> %a) {
+; CHECK-SD-LABEL: fpext_v8f16_v8f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl2 v1.4s, v0.8h
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: fpext_v8f16_v8f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h
+; CHECK-GI-NEXT: ret
+entry:
+ %c = fpext <8 x half> %a to <8 x float>
+ ret <8 x float> %c
+}
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