[llvm] ac3f689 - [InstCombine] Do not assume scalar types in `select`/`zext`

[Antonio Frighetto via llvm-commits]

Author: Antonio Frighetto
Date: 2023-07-23T11:07:13Z
New Revision: ac3f6899f45cfbaf53fa503e4100e92a731b2e7b

URL: https://github.com/llvm/llvm-project/commit/ac3f6899f45cfbaf53fa503e4100e92a731b2e7b
DIFF: https://github.com/llvm/llvm-project/commit/ac3f6899f45cfbaf53fa503e4100e92a731b2e7b.diff

LOG: [InstCombine] Do not assume scalar types in `select`/`zext`

Do not assume scalar types when folding binops of `select`
operations and `zext`/`sext` of their condition.

Reported-by: Benjins, dyung

Proofs: https://alive2.llvm.org/ce/z/GmDLns

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
    llvm/test/Transforms/InstCombine/binop-select-cast-of-select-cond.ll

Removed: 
    


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diff  --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index fbf7d7be81c058..afd6e034f46d70 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -912,8 +912,8 @@ InstCombinerImpl::foldBinOpOfSelectAndCastOfSelectCondition(BinaryOperator &I) {
     if (IsTrueArm) {
       C = Constant::getNullValue(V->getType());
     } else if (IsZExt) {
-      C = Constant::getIntegerValue(
-          V->getType(), APInt(V->getType()->getIntegerBitWidth(), 1));
+      unsigned BitWidth = V->getType()->getScalarSizeInBits();
+      C = Constant::getIntegerValue(V->getType(), APInt(BitWidth, 1));
     } else {
       C = Constant::getAllOnesValue(V->getType());
     }

diff  --git a/llvm/test/Transforms/InstCombine/binop-select-cast-of-select-cond.ll b/llvm/test/Transforms/InstCombine/binop-select-cast-of-select-cond.ll
index d1cec11878616d..eaec15b1672457 100644
--- a/llvm/test/Transforms/InstCombine/binop-select-cast-of-select-cond.ll
+++ b/llvm/test/Transforms/InstCombine/binop-select-cast-of-select-cond.ll
@@ -187,8 +187,8 @@ define i64 @select_non_const_sides(i1 %c, i64 %arg1, i64 %arg2) {
 define i6 @sub_select_sext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF) {
 ; CHECK-LABEL: define i6 @sub_select_sext_op_swapped_non_const_args
 ; CHECK-SAME: (i1 [[C:%.*]], i6 [[ARGT:%.*]], i6 [[ARGF:%.*]]) {
-; CHECK-DAG:     [[TMP1:%.*]] = xor i6 [[ARGT]], -1
-; CHECK-DAG:     [[TMP2:%.*]] = sub i6 0, [[ARGF]]
+; CHECK-NEXT:    [[TMP1:%.*]] = xor i6 [[ARGT]], -1
+; CHECK-NEXT:    [[TMP2:%.*]] = sub i6 0, [[ARGF]]
 ; CHECK-NEXT:    [[SUB:%.*]] = select i1 [[C]], i6 [[TMP1]], i6 [[TMP2]]
 ; CHECK-NEXT:    ret i6 [[SUB]]
 ;
@@ -201,8 +201,8 @@ define i6 @sub_select_sext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF)
 define i6 @sub_select_zext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF) {
 ; CHECK-LABEL: define i6 @sub_select_zext_op_swapped_non_const_args
 ; CHECK-SAME: (i1 [[C:%.*]], i6 [[ARGT:%.*]], i6 [[ARGF:%.*]]) {
-; CHECK-DAG:     [[TMP1:%.*]] = sub i6 1, [[ARGT]]
-; CHECK-DAG:     [[TMP2:%.*]] = sub i6 0, [[ARGF]]
+; CHECK-NEXT:    [[TMP1:%.*]] = sub i6 1, [[ARGT]]
+; CHECK-NEXT:    [[TMP2:%.*]] = sub i6 0, [[ARGF]]
 ; CHECK-NEXT:    [[SUB:%.*]] = select i1 [[C]], i6 [[TMP1]], i6 [[TMP2]]
 ; CHECK-NEXT:    ret i6 [[SUB]]
 ;
@@ -211,3 +211,16 @@ define i6 @sub_select_zext_op_swapped_non_const_args(i1 %c, i6 %argT, i6 %argF)
   %sub = sub i6 %ext, %sel
   ret i6 %sub
 }
+
+define <2 x i8> @vectorized_add(<2 x i1> %c, <2 x i8> %arg) {
+; CHECK-LABEL: define <2 x i8> @vectorized_add
+; CHECK-SAME: (<2 x i1> [[C:%.*]], <2 x i8> [[ARG:%.*]]) {
+; CHECK-NEXT:    [[TMP1:%.*]] = add <2 x i8> [[ARG]], <i8 1, i8 1>
+; CHECK-NEXT:    [[ADD:%.*]] = select <2 x i1> [[C]], <2 x i8> [[TMP1]], <2 x i8> <i8 1, i8 1>
+; CHECK-NEXT:    ret <2 x i8> [[ADD]]
+;
+  %zext = zext <2 x i1> %c to <2 x i8>
+  %sel = select <2 x i1> %c, <2 x i8> %arg, <2 x i8> <i8 1, i8 1>
+  %add = add <2 x i8> %sel, %zext
+  ret <2 x i8> %add
+}