[llvm] 90933c2 - [RISCV] Remove unnecessary opcode argument to FPUnaryOp_imm template. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-22T10:56:04-07:00
New Revision: 90933c257c41eb62d3804ad4f571ae05a1eafc1a

URL: https://github.com/llvm/llvm-project/commit/90933c257c41eb62d3804ad4f571ae05a1eafc1a
DIFF: https://github.com/llvm/llvm-project/commit/90933c257c41eb62d3804ad4f571ae05a1eafc1a.diff

LOG: [RISCV] Remove unnecessary opcode argument to FPUnaryOp_imm template. NFC

Instead of always passing OPC_OP_FP just hardcode it inside.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 9b81ebe6717f40..f36882f9a9689a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -54,7 +54,7 @@ class FPBinaryOp_rr<bits<7> funct7, bits<3> funct3, DAGOperand rdty,
               (ins rsty:$rs1, rsty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-class FPUnaryOp_imm<bits<7> funct7, bits<5> rs2val, bits<3> funct3, RISCVOpcode opcode,
+class FPUnaryOp_imm<bits<7> funct7, bits<5> rs2val, bits<3> funct3,
                     dag outs, dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
   bits<5> imm;
@@ -65,7 +65,7 @@ class FPUnaryOp_imm<bits<7> funct7, bits<5> rs2val, bits<3> funct3, RISCVOpcode
   let Inst{19-15} = imm;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
+  let Inst{6-0} = OPC_OP_FP.Value;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, mayRaiseFPException = 1,
@@ -84,7 +84,7 @@ class FPUnaryOp_r_rtz<bits<7> funct7, bits<5> rs2val, DAGOperand rdty,
 
 let Predicates = [HasStdExtZfa] in {
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def FLI_S : FPUnaryOp_imm<0b1111000, 0b00001, 0b000, OPC_OP_FP, (outs FPR32:$rd),
+def FLI_S : FPUnaryOp_imm<0b1111000, 0b00001, 0b000, (outs FPR32:$rd),
             (ins loadfpimm:$imm), "fli.s", "$rd, $imm">,
             Sched<[WriteFLI32]>;
 
@@ -106,7 +106,7 @@ def FLEQ_S : FPCmp_rr<0b1010000, 0b100, "fleq.s", FPR32>;
 
 let Predicates = [HasStdExtZfa, HasStdExtD] in {
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def FLI_D : FPUnaryOp_imm<0b1111001, 0b00001, 0b000, OPC_OP_FP, (outs FPR64:$rd),
+def FLI_D : FPUnaryOp_imm<0b1111001, 0b00001, 0b000, (outs FPR64:$rd),
             (ins loadfpimm:$imm), "fli.d", "$rd, $imm">,
             Sched<[WriteFLI64]>;
 
@@ -146,7 +146,7 @@ def FMV_X_W_FPR64 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR64,
 
 let Predicates = [HasStdExtZfa, HasStdExtZfhOrZvfh] in
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
-def FLI_H : FPUnaryOp_imm<0b1111010, 0b00001, 0b000, OPC_OP_FP, (outs FPR16:$rd),
+def FLI_H : FPUnaryOp_imm<0b1111010, 0b00001, 0b000, (outs FPR16:$rd),
             (ins loadfpimm:$imm), "fli.h", "$rd, $imm">,
             Sched<[WriteFLI16]>;