[llvm] 0315fca - [AArch64] Move branch relaxation after bbsection assignment
Daniel Hoekwater via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 21 13:25:30 PDT 2023
Author: Daniel Hoekwater
Date: 2023-07-21T20:24:52Z
New Revision: 0315fca9120b84487870412adb8edc586eda704f
URL: https://github.com/llvm/llvm-project/commit/0315fca9120b84487870412adb8edc586eda704f
DIFF: https://github.com/llvm/llvm-project/commit/0315fca9120b84487870412adb8edc586eda704f.diff
LOG: [AArch64] Move branch relaxation after bbsection assignment
Because branch relaxation needs to factor in if branches target
a block in the same section or a different one, it needs to run
after the Basic Block Sections / Machine Function Splitting passes.
Because Jump table compression relies on block offsets remaining
fixed after the table is compressed, we must also move the JT
compression pass.
The only tests affected are ones enforcing just the ordering and
the a few that have basic block ids changed because RenumberBlocks
hasn't run yet.
Differential Revision: https://reviews.llvm.org/D153829
Added:
Modified:
llvm/include/llvm/CodeGen/TargetPassConfig.h
llvm/lib/CodeGen/TargetPassConfig.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/test/CodeGen/AArch64/O0-pipeline.ll
llvm/test/CodeGen/AArch64/O3-pipeline.ll
llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
llvm/test/CodeGen/AArch64/seh_funclet_x1.ll
llvm/test/CodeGen/AArch64/wineh-try-catch.ll
llvm/test/DebugInfo/AArch64/fallthrough-branch.ll
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h
index 8d7086d02c8ac2..9cdd9e30a361b3 100644
--- a/llvm/include/llvm/CodeGen/TargetPassConfig.h
+++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h
@@ -438,6 +438,10 @@ class TargetPassConfig : public ImmutablePass {
/// immediately before machine code is emitted.
virtual void addPreEmitPass() { }
+ /// This pass may be implemented by targets that want to run passes
+ /// immediately after basic block sections are assigned.
+ virtual void addPostBBSections() {}
+
/// Targets may add passes immediately before machine code is emitted in this
/// callback. This is called even later than `addPreEmitPass`.
// FIXME: Rename `addPreEmitPass` to something more sensible given its actual
diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp
index 5d418c6d97bc0e..98ea2f21b3c807 100644
--- a/llvm/lib/CodeGen/TargetPassConfig.cpp
+++ b/llvm/lib/CodeGen/TargetPassConfig.cpp
@@ -1278,6 +1278,8 @@ void TargetPassConfig::addMachinePasses() {
addPass(createMachineFunctionSplitterPass());
}
+ addPostBBSections();
+
if (!DisableCFIFixup && TM->Options.EnableCFIFixup)
addPass(createCFIFixup());
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
index 0c017bce8aaa27..559879139758ba 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
@@ -526,6 +526,7 @@ class AArch64PassConfig : public TargetPassConfig {
void addPostRegAlloc() override;
void addPreSched2() override;
void addPreEmitPass() override;
+ void addPostBBSections() override;
void addPreEmitPass2() override;
std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
@@ -815,11 +816,6 @@ void AArch64PassConfig::addPreEmitPass() {
if (EnableBranchTargets)
addPass(createAArch64BranchTargetsPass());
- // Relax conditional branch instructions if they're otherwise out of
- // range of their destination.
- if (BranchRelaxation)
- addPass(&BranchRelaxationPassID);
-
if (TM->getTargetTriple().isOSWindows()) {
// Identify valid longjmp targets for Windows Control Flow Guard.
addPass(createCFGuardLongjmpPass());
@@ -827,14 +823,21 @@ void AArch64PassConfig::addPreEmitPass() {
addPass(createEHContGuardCatchretPass());
}
- if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
- addPass(createAArch64CompressJumpTablesPass());
-
if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&
TM->getTargetTriple().isOSBinFormatMachO())
addPass(createAArch64CollectLOHPass());
}
+void AArch64PassConfig::addPostBBSections() {
+ // Relax conditional branch instructions if they're otherwise out of
+ // range of their destination.
+ if (BranchRelaxation)
+ addPass(&BranchRelaxationPassID);
+
+ if (TM->getOptLevel() != CodeGenOpt::None && EnableCompressJumpTables)
+ addPass(createAArch64CompressJumpTablesPass());
+}
+
void AArch64PassConfig::addPreEmitPass2() {
// SVE bundles move prefixes with destructive operations. BLR_RVMARKER pseudo
// instructions are lowered to bundles as well.
diff --git a/llvm/test/CodeGen/AArch64/O0-pipeline.ll b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
index b04998348dd055..90a61cc6d928ab 100644
--- a/llvm/test/CodeGen/AArch64/O0-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O0-pipeline.ll
@@ -72,11 +72,11 @@
; CHECK-NEXT: Implement the 'patchable-function' attribute
; CHECK-NEXT: Workaround A53 erratum 835769 pass
; CHECK-NEXT: AArch64 Branch Targets
-; CHECK-NEXT: Branch relaxation pass
; CHECK-NEXT: Contiguously Lay Out Funclets
; CHECK-NEXT: StackMap Liveness Analysis
; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: Machine Sanitizer Binary Metadata
+; CHECK-NEXT: Branch relaxation pass
; CHECK-NEXT: Insert CFI remember/restore state instructions
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
diff --git a/llvm/test/CodeGen/AArch64/O3-pipeline.ll b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
index 92004996297dae..fae6b23bf737c3 100644
--- a/llvm/test/CodeGen/AArch64/O3-pipeline.ll
+++ b/llvm/test/CodeGen/AArch64/O3-pipeline.ll
@@ -218,14 +218,14 @@
; CHECK-NEXT: Machine Copy Propagation Pass
; CHECK-NEXT: Workaround A53 erratum 835769 pass
; CHECK-NEXT: AArch64 Branch Targets
-; CHECK-NEXT: Branch relaxation pass
-; CHECK-NEXT: AArch64 Compress Jump Tables
; CHECK-NEXT: Contiguously Lay Out Funclets
; CHECK-NEXT: StackMap Liveness Analysis
; CHECK-NEXT: Live DEBUG_VALUE analysis
; CHECK-NEXT: Machine Sanitizer Binary Metadata
; CHECK-NEXT: Machine Outliner
; CHECK-NEXT: FunctionPass Manager
+; CHECK-NEXT: Branch relaxation pass
+; CHECK-NEXT: AArch64 Compress Jump Tables
; CHECK-NEXT: Insert CFI remember/restore state instructions
; CHECK-NEXT: Lazy Machine Block Frequency Analysis
; CHECK-NEXT: Machine Optimization Remark Emitter
diff --git a/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll b/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
index 2b826b208f5510..9dfe84c46e9f9f 100644
--- a/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-opt-remarks-lazy-bfi.ll
@@ -34,6 +34,14 @@
; HOTNESS-NEXT: Executing Pass 'Function Pass Manager'
; HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
; HOTNESS-NEXT: Freeing Pass 'Verify generated machine code'
+; HOTNESS-NEXT: Executing Pass 'Branch relaxation pass' on Function 'empty_func'
+; HOTNESS-NEXT: Freeing Pass 'Branch relaxation pass' on Function 'empty_func'
+; HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
+; HOTNESS-NEXT: Freeing Pass 'Verify generated machine code'
+; HOTNESS-NEXT: Executing Pass 'AArch64 Compress Jump Tables' on Function 'empty_func'
+; HOTNESS-NEXT: Freeing Pass 'AArch64 Compress Jump Tables' on Function 'empty_func'
+; HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
+; HOTNESS-NEXT: Freeing Pass 'Verify generated machine code'
; HOTNESS-NEXT: Executing Pass 'Insert CFI remember/restore state instructions' on Function 'empty_func'
; HOTNESS-NEXT: Freeing Pass 'Insert CFI remember/restore state instructions' on Function 'empty_func'
; HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
@@ -59,6 +67,14 @@
; NO_HOTNESS-NEXT: Executing Pass 'Function Pass Manager'
; NO_HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
; NO_HOTNESS-NEXT: Freeing Pass 'Verify generated machine code'
+; NO_HOTNESS-NEXT: Executing Pass 'Branch relaxation pass' on Function 'empty_func'
+; NO_HOTNESS-NEXT: Freeing Pass 'Branch relaxation pass' on Function 'empty_func'
+; NO_HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
+; NO_HOTNESS-NEXT: Freeing Pass 'Verify generated machine code'
+; NO_HOTNESS-NEXT: Executing Pass 'AArch64 Compress Jump Tables' on Function 'empty_func'
+; NO_HOTNESS-NEXT: Freeing Pass 'AArch64 Compress Jump Tables' on Function 'empty_func'
+; NO_HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
+; NO_HOTNESS-NEXT: Freeing Pass 'Verify generated machine code'
; NO_HOTNESS-NEXT: Executing Pass 'Insert CFI remember/restore state instructions' on Function 'empty_func'
; NO_HOTNESS-NEXT: Freeing Pass 'Insert CFI remember/restore state instructions' on Function 'empty_func'
; NO_HOTNESS-NEXT: Executing Pass 'Verify generated machine code'
diff --git a/llvm/test/CodeGen/AArch64/seh_funclet_x1.ll b/llvm/test/CodeGen/AArch64/seh_funclet_x1.ll
index abb924933b9038..eb96157e221963 100644
--- a/llvm/test/CodeGen/AArch64/seh_funclet_x1.ll
+++ b/llvm/test/CodeGen/AArch64/seh_funclet_x1.ll
@@ -3,8 +3,8 @@
; Windows runtime passes the establisher frame as the second argument to the
; termination handler. Check that we copy it into fp.
-; CHECK: ?dtor$3@?0?main at 4HA":
-; CHECK: .seh_proc "?dtor$3@?0?main at 4HA"
+; CHECK: ?dtor$6@?0?main at 4HA":
+; CHECK: .seh_proc "?dtor$6@?0?main at 4HA"
; CHECK: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
; CHECK-NEXT: .seh_save_fplr_x 16
; CHECK-NEXT: .seh_endprologue
diff --git a/llvm/test/CodeGen/AArch64/wineh-try-catch.ll b/llvm/test/CodeGen/AArch64/wineh-try-catch.ll
index af9491aaf346d0..b27e5374b25762 100644
--- a/llvm/test/CodeGen/AArch64/wineh-try-catch.ll
+++ b/llvm/test/CodeGen/AArch64/wineh-try-catch.ll
@@ -44,7 +44,7 @@
; CHECK: [[CATCHRETDEST:.LBB0_[0-9]+]]: // %catchret.dest
; Check the catch funclet.
-; CHECK-LABEL: "?catch$2@?0??func@@YAHXZ at 4HA":
+; CHECK-LABEL: "?catch$4@?0??func@@YAHXZ at 4HA":
; Check that the stack space is allocated only for the callee saved registers.
; CHECK: stp x19, x20, [sp, #-48]!
@@ -66,7 +66,7 @@
; CHECK: stur w8, [x29, [[X_OFFSET]]]
; Check that the funclet branches back to the catchret destination
-; CHECK: adrp x0, .LBB0_3
+; CHECK: adrp x0, .LBB0_2
; CHECK-NEXT: add x0, x0, [[CATCHRETDEST]]
@@ -91,7 +91,7 @@
; UNWIND-NEXT: ; str x21, [sp, #16]
; UNWIND-NEXT: ; stp x19, x20, [sp, #-64]!
; UNWIND-NEXT: ; end
-; UNWIND: Function: ?catch$2@?0??func@@YAHXZ at 4HA
+; UNWIND: Function: ?catch$4@?0??func@@YAHXZ at 4HA
; UNWIND: Prologue [
; UNWIND-NEXT: ; stp x29, x30, [sp, #32]
; UNWIND-NEXT: ; str x28, [sp, #24]
diff --git a/llvm/test/DebugInfo/AArch64/fallthrough-branch.ll b/llvm/test/DebugInfo/AArch64/fallthrough-branch.ll
index 3873f7fe61370a..c224a75cf14106 100644
--- a/llvm/test/DebugInfo/AArch64/fallthrough-branch.ll
+++ b/llvm/test/DebugInfo/AArch64/fallthrough-branch.ll
@@ -10,16 +10,17 @@ define swiftcc void @"$s1t1f1bySb_tF"(i1 %0) !dbg !35 {
%3 = bitcast i1* %2 to i8*
call void @llvm.memset.p0i8.i64(i8* align 8 %3, i8 0, i64 1, i1 false)
store i1 %0, i1* %2, align 8, !dbg !37
-; CHECK: B %bb.1, debug-location !{{[0-9]+}}
+; CHECK: B %[[BB4:bb\.[0-9]+]], debug-location !{{[0-9]+}}
br i1 %0, label %4, label %5, !dbg !38
4: ; preds = %1
+; CHECK: [[BB4]]
; Check that at -O0 the branches and their debug locations are not eliminated.
-; CHECK: B %bb.3, debug-location !{{[0-9]+}}
+; CHECK: B %[[BB6:bb\.[0-9]+]], debug-location !{{[0-9]+}}
br label %6, !dbg !39
5: ; preds = %1
-; CHECK: B %bb.3, debug-location !{{[0-9]+}}
+; CHECK: B %[[BB6]], debug-location !{{[0-9]+}}
br label %6, !dbg !40
6: ; preds = %4, %5
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