[llvm] c41a62e - [AMDGPU] [NFC] Fixed a typo in SIShrinkInstructions.cpp

[Pranav Taneja via llvm-commits]

Author: Pranav Taneja
Date: 2023-07-21T15:35:19+05:30
New Revision: c41a62e924622573a32c6e856d3afe76e61a6160

URL: https://github.com/llvm/llvm-project/commit/c41a62e924622573a32c6e856d3afe76e61a6160
DIFF: https://github.com/llvm/llvm-project/commit/c41a62e924622573a32c6e856d3afe76e61a6160.diff

LOG: [AMDGPU] [NFC] Fixed a typo in SIShrinkInstructions.cpp

Reviewed By: pravinjagtap

Differential Revision: https://reviews.llvm.org/D155785

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
index 7f46dcc96478ff..4159dc694c1e03 100644
--- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -476,7 +476,7 @@ void SIShrinkInstructions::shrinkMadFma(MachineInstr &MI) const {
   }
 }
 
-/// Attempt to shink AND/OR/XOR operations requiring non-inlineable literals.
+/// Attempt to shrink AND/OR/XOR operations requiring non-inlineable literals.
 /// For AND or OR, try using S_BITSET{0,1} to clear or set bits.
 /// If the inverse of the immediate is legal, use ANDN2, ORN2 or
 /// XNOR (as a ^ b == ~(a ^ ~b)).