[PATCH] D155928: [RISCV] Add patterns for vnsrl.vx where shift amount is truncated

[Luke Lau via Phabricator via llvm-commits]

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Similar to D155698 <https://reviews.llvm.org/D155698> where the shift amount is extended, this patch extends the
ComplexPattern to handle the case where the shift amount has been truncated.
Truncations are custom lowered to truncate_vector_vl, and in cases like i64 ->
i16 they are truncated by one power of two at a time, so we need to unravel
nested layers of them.

The pattern can also be reused for Zvbb's vwsll.vx in an upcoming patch.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155928

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

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