[llvm] f6bdfb0 - [RISCV] Remove VPatBinaryExtVL_WV_WX multiclass. NFC
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 21 02:13:39 PDT 2023
Author: Luke Lau
Date: 2023-07-21T10:13:30+01:00
New Revision: f6bdfb0b92690403ceef8c1d58adf7a3a733b543
URL: https://github.com/llvm/llvm-project/commit/f6bdfb0b92690403ceef8c1d58adf7a3a733b543
DIFF: https://github.com/llvm/llvm-project/commit/f6bdfb0b92690403ceef8c1d58adf7a3a733b543.diff
LOG: [RISCV] Remove VPatBinaryExtVL_WV_WX multiclass. NFC
It's no longer needed now that the sext/zext patterns have been merged.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D155815
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 8cef4140067904..da095a48a90441 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -1431,7 +1431,7 @@ multiclass VPatReductionVL_RM<SDNode vop, string instruction_name, bit is_float>
}
}
-multiclass VPatBinaryExtVL_WV_WX<SDNode op, string instruction_name> {
+multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti;
@@ -1458,26 +1458,17 @@ multiclass VPatBinaryExtVL_WV_WX<SDNode op, string instruction_name> {
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
(vti.Vector (IMPLICIT_DEF)),
wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
- }
- }
-}
-multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name>
- : VPatBinaryExtVL_WV_WX<op, instruction_name> {
- foreach vtiToWti = AllWidenableIntVectors in {
- defvar vti = vtiToWti.Vti;
- defvar wti = vtiToWti.Wti;
- let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
- GetVTypePredicates<wti>.Predicates) in
- def : Pat<
- (vti.Vector
- (riscv_trunc_vector_vl
- (op (wti.Vector wti.RegClass:$rs2),
- (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask),
- VLOpFrag)),
- (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
- (vti.Vector (IMPLICIT_DEF)),
- wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ def : Pat<
+ (vti.Vector
+ (riscv_trunc_vector_vl
+ (op (wti.Vector wti.RegClass:$rs2),
+ (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask),
+ VLOpFrag)),
+ (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
+ (vti.Vector (IMPLICIT_DEF)),
+ wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
+ }
}
}
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