[PATCH] D153721: [RISCV] Add support for XCVsimd extension in CV32E40P

[Funan Zeng via Phabricator via llvm-commits]

melonedo updated this revision to Diff 542780.
melonedo added a comment.

Switch cv.and/or/xor to signed according to spec to allow 0xffff-like patterns


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153721/new/

https://reviews.llvm.org/D153721

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/corev/XCVsimd-invalid.s
  llvm/test/MC/RISCV/corev/XCVsimd.s

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