[PATCH] D153234: [RISCV] Add codegen for Zfbfmin instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td:34
+def riscv_fmv_h_x_bf16
+    : SDNode<"RISCVISD::FMV_H_X", SDT_RISCVFMV_H_X_BF16>;
+def riscv_fmv_x_anyexth_bf16
----------------
There's only supposed to be one `SDNode` declaration per `RISCVISD` opcode name. The `SDTypeProfile` for the existing version needs to be changed to `SDTCisFP` instead of `SDTCisVT<1, f16>`. The semantics of the opcode changed, so the type description needs to change accordingly.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153234/new/

https://reviews.llvm.org/D153234