[llvm] a70aa5e - [RISCV] precommit for removing useless copy from undef subreg

[Piyou Chen via llvm-commits]

Author: Piyou Chen
Date: 2023-07-20T20:38:24-07:00
New Revision: a70aa5ea7c836b12fb587b8682225e4bbfe56c37

URL: https://github.com/llvm/llvm-project/commit/a70aa5ea7c836b12fb587b8682225e4bbfe56c37
DIFF: https://github.com/llvm/llvm-project/commit/a70aa5ea7c836b12fb587b8682225e4bbfe56c37.diff

LOG: [RISCV] precommit for removing useless copy from undef subreg

testcase from https://github.com/llvm/llvm-project/issues/63554

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D155039

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
index 4882add84b5bff..336136c0aa28c2 100644
--- a/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/undef-earlyclobber-chain.ll
@@ -145,3 +145,18 @@ declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
 declare <vscale x 1 x i16> @llvm.experimental.stepvector.nxv1i16()
 declare <vscale x 8 x i16> @llvm.vector.insert.nxv8i16.nxv1i16(<vscale x 8 x i16>, <vscale x 1 x i16>, i64 immarg)
 declare <vscale x 8 x i8> @llvm.riscv.vrgatherei16.vv.nxv8i8.i64(<vscale x 8 x i8>, <vscale x 8 x i8>, <vscale x 8 x i16>, i64)
+
+
+define void @repeat_shuffle(<2 x double> %v, ptr noalias %q) {
+; CHECK-LABEL: repeat_shuffle:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmv2r.v v12, v8
+; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-NEXT:    vmv1r.v v13, v10
+; CHECK-NEXT:    vslideup.vi v8, v12, 2
+; CHECK-NEXT:    vse64.v v8, (a0)
+; CHECK-NEXT:    ret
+  %w = shufflevector <2 x double> %v, <2 x double> poison, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
+  store <4 x double> %w, ptr %q
+  ret void
+}